Kevin Jorrey
2101 Winding
Way Lane (Home)
972-562-1921
Allen, TX 75002 kjorrey@comcast.net (Cell) 972-567-5950
Electronics Engineer
Over 15 years of
professional experience in semiconductor design, implementation, and design
tool flows. Eight years in IC design and implementation and
seven years in Technical Field Support and Management.
PROFESSIONAL Experience
Mentor Graphics
Corporation, Addison, TX 2002-2003
Manager
of the Americas, Application Engineers
Led a team of 13 AE’s in supporting pre and post sales activity for Mentor emulation
products.
¨
Worked closely with Mentor management during the
integration of IKOS personnel, process, and product to assure we kept the IKOS
customers supported.
¨
Managed all emulation projects within the region, ensuring the proper
resources were available to be successful.
¨
Reviewed all Statement of Works for completeness and risk in the
evaluation.
¨
Recruited and coached team members, obtaining a 90% retention rate.
IKOS SYSTEMS, INC., Richardson, TX 1996-2002
Director
of North
America Technical Services (2000-2002)
Directed five managers and 25 engineers throughout the Americas. Mentor Graphics acquired
IKOS Systems in May 2002.
¨
Managed a $4M budget with full P&L responsibility.
¨
Helped grow the company from a $25M to $60M by managing the technical
pre-sales process.
¨
Achieved major technical benchmark wins at Broadcom, Intel, Lucent,
ATI, nVidia and others generating over $40M in new business.
¨
Managed an internal Customer Support Group that provided email and
phone support to our customers.
¨
Responsible for weekly attendance in the product and customer forums
and served as a consistent voice back to the field for key product and customer
situations.
¨
Worked with engineering and product marketing to develop next
generation product functional specs.
¨
Contracted with outside consulting firms for extra resources during
peak times.
¨
Supported Alpha/Beta testing programs for the company’s new Co-Modeling
products.
¨
Established strategies and procedures for IT infrastructure to support
remote offices.
¨
Participated in industry trade shows, in both planning and presenting
demos.
Eastern
Region Technical Services Manager (1996-2000)
Led a team of eight AE’s in supporting pre and post sales activity for
IKOS systems acceleration and emulation products. Hands on
manager as well as an individual contributor.
¨
Established and managed programs to support pre and post-sales efforts.
¨
Developed and presented technical presentations featuring current
products and products under development.
¨
Performed complex library and memory modeling to be used in emulation
and simulation.
¨
Consulted customers on design guidelines and methodologies for
efficient Emulation.
¨
Experienced in interfacing with various target systems such as ARM
emulator, TI XDS, and MII traffic generators.
¨
Successfully emulated several complex and very large ASICs mostly
Graphics, Multi-media, and ATM ASICs
¨
Found many functional bugs and communicated solutions back to the RTL
designers.
¨
Provided customer training on simulation and emulation products.
¨
Installed product software and hardware on Sun and HP workstations.
¨
Established and maintained strong customer relationships by delivering
outstanding customer support.
¨
Managed eight FAE’s in five field offices, covering 28 states and Canada.
¨
Tools used: IKOS Voyager, Cadence VerilogXL, SynopsysDC, SynopsysVCS,
and MS Office Suite.
TEXAS INSTRUMENTS, INC., Richardson, TX 1980-1996
ASIC
Design Engineer, PCI group (1994-1996)
Responsible for Block Definition, RTL coding, Synthesys, Simulation, and
Place and Route of PCI to PCMCIA Bridge Chips.
¨
Implemented architectural specifications using VHDL coding.
¨
Supported PCI, PCMCIA, Cardbus, and I2C bus interfaces.
¨
Used motive static timing tool to determine critical paths.
¨
Visited external customers in support of the product.
¨
Tools used: Synopsys, Cadence, VHDL, Verilog, Sun, Perl, and C
programming.
ASIC
Design Engineer, Defense Group (1992-1994)
Responsible
for Synthesys, Simulation, Place and Route and Silicon debug of ASIC used in
the F-16 Weapons Computer.
¨
Led a design team of three Engineers.
Delegated tasks to each team member based on the engineer’s capabilities
and expertise.
¨
Defined System Level Timing, Clock Specifications, and Synthesis
Constraints for timing critical input and output signals.
¨
Defined synthesis guidelines and synthesize design to timing
specifications.
¨
Supported Mil-Std-1553 bus, Memory interface and proprietary bus.
¨
Tools used: Synopsys, Cadence, Zycad, VHDL, Apollo, Sun, Perl, and C
programming.
Memory
IC Design Engineer, ASIC Group (1988-1992)
Responsible for transistor level design of memories used in Texas
Instruments BiCMOS ASIC library.
¨
Performed Design Rule Check (DRC) Verification and Layout versus
Schematic (LVS) Verification.
¨
Fully characterized memories for use in TI ASIC flow using SPICE and
statistical analysis tool.
¨
Project lead for a multi-port BiCMOS memory compiler used in ASIC
products.
¨
Performed design duties for a customer defined memory module that was
part of a custom telecommunications chip.
¨
Re-designed a 256k ECL I/O BiCMOS SRAM product to a newer technology,
extending the life of the product.
¨
Tools used: TI internal schematics capture tools, SPICE, Mentor GDT
layout/simulator, and Cadence EDGE.
Front
End Wafer Technician, Semiconductor Group (1980-1988)
¨
Maintained implant, diffusion, etch equipment
and test probe used in wafer fabrication.
EDUCATION
MSEE, Southern Methodist University, Dallas, TX
BSEE, Southern Methodist University, Dallas, TX
Professional Development
Nahman-Parsons, “Selling the
Value of Technology”
Telecommunications Research
Associates, “Understanding Emerging
Technologies in the New Millennium”
Associations
IEEE
MILITARY
United States Navy, Aviation Fire Control
Technician,
Maintained the A-7 APQ radar
and Heads up Display system
