Lab 1 Report

Abstract:
In this lab, we wrote a Verilog code to implement a 4:1 mux. We used two types of logic simulators to verify its functionality. They were Modelsim and Xilinx Foundation Series. The Modelsim's simulator showed that the code functions correctly with all the delay included. As for the Xilinx's simulator, we simulated the mux using functional and timing mode. The result showed that the it is implement correctly as a functional wise, but under the timing mode it showed longer propagation delay than the code was written for. The code was written for the worst case delay to be about 5ns, but the output waveform reported to be 10.6ns delay.

Introduction:
The purpose of this lab is to explore the new type of hardware language called Verilog.

Theory:
As the text stated, a hardware description language (HDL) is a computer-based programming language having special constructs and semantics to model, represent, and simulate the functional behavior and timing of digital hardware. Verilog is a hardware description language that can be used to model digital system. It can model many level of abstraction ranging from algorithmic level to gate level to switch level.
As a beginner, we started out with the basic 4:1 mux. We written the code in the format of structural description using the primitive gates. In addition, we included the gate delays to model a more realistic physical hardware device. Finally, we simulated the mux using Modelsim and Xilinx package to analyze the result.

Conclusion:
The result showed that by using the Modelsim's simulator we only need to simulate one mode, its default mode to implement whichever the Verilog code was intended to behave. In contrast, the Xilinx's logic simulator has several different modes to simulate. They are functional, timing, glitch, and unit. For the purpose of this lab, we only consider the functional and timing mode. Under the functional mode the simulator only consider the functional wise and do not include the timing delay whereas the timing mode includes the specify delays that the code was written for. The result of Xilinx's simulator showed that the code is function correctly; however, the timing mode did not showed the correct gate delay as specify in the Verilog code. Perhaps the timing mode includes some other additional delays that we do not aware of.
As far as the complexity between the two logic simulators, Xilinx package is simpler to use. Modelsim required numerous steps whereas the Xilinx package is a single click to away toward the result. Xilinx's simulator has a built-in keyboard toggle switch that is switching between logical 0 and 1 every time the appropriate keyboard key is pressed. Also, Xilinx's simulator has the form section so that formula can be entered. Moreover, it do runs a script file similar to the do file in the Modelsim. In essence, Xilinx's simulator is much more advanced than Modelsim because it has numerous way to simulate its Verilog HDL.