Lab 2 Report
Introduction
This lab assignment consists of a Verilog code to implement an
ascii coded string (hexadecimal or a decimal) to a binary
coded decimal/binary converter. The converter includes a
32-bit input bus that carry a hexadecimal values and a
control signal (d2b). The converter's output is a 16-bit
bus which will carry an ascii coded hexadecimal when the
d2b is 0; otherwise, the converter will treat the asccii
code as a decimal values and then converts it to a
hexadecimal. This converter assumes that the user
provides a valid input data; otherwise, the converter
will give an invalid output. The valid data is a 32-bit
bus that will be divided into 4 bytes and each byte will
only limit to carry the hexadecimal values ranging
between 30 to 39 and 41 to 46. If the user provides
anything other than these values, the converter will not
guarantee to return the correct output.
Approach
The scheme of this project is to partition the converter
into several modules and then puts it in the format of
hierarchical decomposition. Each module will be implement
and simulate as an independent project. Once these
modules had been build and tested, the top- level module
will be instantiate the necessary modules to complete the
task.
Procedure
This assignment requires the use of Xilinx Foundation
series software tools to implement it and performs its
functional and timing simulations. The converter is
formatted in a hierarchical decomposition model. The
top-level module contains four module (ascii_conv_8)
instantiations of a byte input conversion, plus a decimal
to hexadecimal conversion module (dec2hex) instantiation
using the output of the "ascii_conv_8" as its
input. Moreover, the top module includes a 2x1 mux which
will select the desired conversion to the output bus. The
"ascii_conv_8" module take on a byte input data
and then assigns its ascii coded string. The other
"dec2hex" module consists of three addition ROM
memories nested within its module. The
"dec2hex" module functions as a adder of these
three ROM devices to produce a desired conversion from
decimal to hexadecimal values. The lowest level module is
the three ROM table assignment. They are conv_R1,
conv_R2, and conv_R3.
Simulation Results
The waveforms showed that the converter functions
correctly as long as the user provides the valid input
data (see above input specifications). If the control
signal "d2b" is asserted and the input data
that carry within it a data a byte of value between 41
through 46 will result an invalid output data. The result
of the timing simulation showed a wide range of delay.
The delay ranges as low as 17.6ns and as high as 30.6ns.
The typical delay is approximated to be around 25ns. The
following are the results of a random input values that
the converter generated.
Inputs d2b Outputs Delays Cases
39393939 1 270F 30.6ns worst-case delay
30303030 1 0000 29.8ns best-case delay
30303030 0 0000 17.6ns best-case delay
46464646 0 FFFF 25.2ns worst-case delay
35333231 1 14C9 24.8ns typical
35333231 0 7890 27.6ns typical
Analysis
The above table showed that the worst-case delay occur
when the control signal "d2b" is
asserted in which the delays is the longest (30.6ns). It
is a fact that the worst delay should occur
when "d2b" is asserted because the converter
has to do additional computation. In essence, the
best delay is expected to occur when the "d2b"
is unasserted and the result showed that it is true.
It only takes 17.6ns to generate its output.
Feature Identification
After trying out the Verilog code under Modelsim's
simulator and Xilinx's simulator, an
observation suggests that when using Modelsim's simulator
the output port of a module
instantiation must be declared to be net, not register.
If the output port of the module
instantiation is declared to be a "reg", an
message such as "Illegal output port
assignment" will
be displayed. However, Xilinx software accepts the output
port of the module instantiation to be
a "reg" with the condition that its output port
must be used within another form of procedural
assignment.
Conclusion
The result showed that the converter is function
correctly. However, the converter will
produce an invalid output if the user provides the data
that is outside the range of its
specification. This converter can be improved so that it
will detect an invalid data has been
entered; however, that is beyond the scope of our study
right now.
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