module toplevel (clock,nclr,I0,I1,I2,S0,S1,S2,S3,S4,S5,S6) ;
//input
input clock ;
input nclr,I0,I1,I2;
//output
output S0 ;
output S1 ;
output S2 ;
output S3 ;
output S4 ;
output S5 ;
output S6 ;
// add your declarations here
reg [31:0] count;
reg timer;
reg S0,S1,S2,S3,S4,S5,S6;
reg [3:0] count_out;
reg [3:0] next_count;
//instantiations
//assignment
// add your code here
//generate clock pulse for BCD 7-seg display
//switch the timer pulse at every 6mil count
//clock is driven by 12Mhz oscillator
always @ (negedge nclr or negedge clock)
if (nclr==0)
begin
count=32'h0;
timer=0;
end
else
begin
count=count+1;
if (count==32'h5B8D80)
begin
count=32'h0;
timer=~timer;
end
else timer =0;
end
//generate the counting sequence according to input mode
//input 000 hold the counter at 5
//input 001 up from 1 to 9
//input 010 up from 3 to B every alternate
//input 011 up from 2 to E every alternate
//input 100 down from F to 3
//input 101 down from 9 to 1 every alternate
//input 110 down from C to 0 every alternate
//input 111 plain down counter
always @ (negedge nclr or negedge timer)
if (nclr==0) count_out=4'h0; else count_out=next_count;
always @ (count_out or I0 or I1 or I2) begin
case (count_out)
0 : case ({I2,I1,I0})
0 : next_count = 4'h5;
1 : next_count = 4'h1;
2 : next_count = 4'h3;
3 : next_count = 4'h2;
4 : next_count = 4'hF;
5 : next_count = 4'h9;
6 : next_count = 4'hC;
7 : next_count = 4'hF;
default next_count = 4'h5; endcase
1 : case ({I2,I1,I0})
0 : next_count = 4'h5;
1 : next_count = 4'h2;
2 : next_count = 4'h3;
3 : next_count = 4'h2;
4 : next_count = 4'hF;
5 : next_count = 4'h9;
6 : next_count = 4'h0;
7 : next_count = 4'h0;
default next_count = 4'h5; endcase
2 : case ({I2,I1,I0})
0 : next_count = 4'h5;
1 : next_count = 4'h3;
2 : next_count = 4'h3;
3 : next_count = 4'h4;
4 : next_count = 4'hF;
5 : next_count = 4'h1;
6 : next_count = 4'h0;
7 : next_count = 4'h1;
default next_count = 4'h5; endcase
3 : case ({I2,I1,I0})
0 : next_count = 4'h5;
1 : next_count = 4'h4;
2 : next_count = 4'h5;
3 : next_count = 4'h4;
4 : next_count = 4'hF;
5 : next_count = 4'h1;
6 : next_count = 4'h2;
7 : next_count = 4'h2;
default next_count = 4'h5; endcase
4 : case ({I2,I1,I0})
0 : next_count = 4'h5;
1 : next_count = 4'h5;
2 : next_count = 4'h5;
3 : next_count = 4'h6;
4 : next_count = 4'h3;
5 : next_count = 4'h3;
6 : next_count = 4'h2;
7 : next_count = 4'h3;
default next_count = 4'h5; endcase
5 : case ({I2,I1,I0})
0 : next_count = 4'h5;
1 : next_count = 4'h6;
2 : next_count = 4'h7;
3 : next_count = 4'h6;
4 : next_count = 4'h4;
5 : next_count = 4'h3;
6 : next_count = 4'h4;
7 : next_count = 4'h4;
default next_count = 4'h5; endcase
6 : case ({I2,I1,I0})
0 : next_count = 4'h5;
1 : next_count = 4'h7;
2 : next_count = 4'h7;
3 : next_count = 4'h8;
4 : next_count = 4'h5;
5 : next_count = 4'h5;
6 : next_count = 4'h4;
7 : next_count = 4'h5;
default next_count = 4'h5; endcase
7 : case ({I2,I1,I0})
0 : next_count = 4'h5;
1 : next_count = 4'h8;
2 : next_count = 4'h9;
3 : next_count = 4'h8;
4 : next_count = 4'h6;
5 : next_count = 4'h5;
6 : next_count = 4'h6;
7 : next_count = 4'h6;
default next_count = 4'h5; endcase
8 : case ({I2,I1,I0})
0 : next_count = 4'h5;
1 : next_count = 4'h9;
2 : next_count = 4'h9;
3 : next_count = 4'hA;
4 : next_count = 4'h7;
5 : next_count = 4'h7;
6 : next_count = 4'h6;
7 : next_count = 4'h7;
default next_count = 4'h5; endcase
9 : case ({I2,I1,I0})
0 : next_count = 4'h5;
1 : next_count = 4'h1;
2 : next_count = 4'hB;
3 : next_count = 4'hA;
4 : next_count = 4'h8;
5 : next_count = 4'h7;
6 : next_count = 4'h8;
7 : next_count = 4'h8;
default next_count = 4'h5; endcase
4'hA : case ({I2,I1,I0})
0 : next_count = 4'h5;
1 : next_count = 4'h1;
2 : next_count = 4'hB;
3 : next_count = 4'hC;
4 : next_count = 4'h9;
5 : next_count = 4'h9;
6 : next_count = 4'h8;
7 : next_count = 4'h9;
default next_count = 4'h5; endcase
4'hB : case ({I2,I1,I0})
0 : next_count = 4'h5;
1 : next_count = 4'h1;
2 : next_count = 4'h3;
3 : next_count = 4'hC;
4 : next_count = 4'hA;
5 : next_count = 4'h9;
6 : next_count = 4'hA;
7 : next_count = 4'hA;
default next_count = 4'h5; endcase
4'hC : case ({I2,I1,I0})
0 : next_count = 4'h5;
1 : next_count = 4'h1;
2 : next_count = 4'h3;
3 : next_count = 4'hE;
4 : next_count = 4'hB;
5 : next_count = 4'h9;
6 : next_count = 4'hA;
7 : next_count = 4'hB;
default next_count = 4'h5; endcase
4'hD : case ({I2,I1,I0})
0 : next_count = 4'h5;
1 : next_count = 4'h1;
2 : next_count = 4'h3;
3 : next_count = 4'hE;
4 : next_count = 4'hC;
5 : next_count = 4'h9;
6 : next_count = 4'hC;
7 : next_count = 4'hC;
default next_count = 4'h5; endcase
4'hE : case ({I2,I1,I0})
0 : next_count = 4'h5;
1 : next_count = 4'h1;
2 : next_count = 4'h3;
3 : next_count = 4'h2;
4 : next_count = 4'hD;
5 : next_count = 4'h9;
6 : next_count = 4'hC;
7 : next_count = 4'hD;
default next_count = 4'h5; endcase
4'hF : case ({I2,I1,I0})
0 : next_count = 4'h5;
1 : next_count = 4'h1;
2 : next_count = 4'h3;
3 : next_count = 4'h2;
4 : next_count = 4'hD;
5 : next_count = 4'h9;
6 : next_count = 4'hC;
7 : next_count = 4'hE;
default next_count = 4'h5; endcase
default next_count = 4'h9;
endcase
end
//BCD 7-segment display
//
// S6__
//S5| |S4
// |_S3|
//S2| |S1
// |_S0|
//
always @ (count_out)
begin
case (count_out)
0 : begin S0=1;S1=1;S2=1;S3=0;S4=1;S5=1;S6=1; end
1 : begin S0=0;S1=1;S2=0;S3=0;S4=1;S5=0;S6=0; end
2 : begin S0=1;S1=0;S2=1;S3=1;S4=1;S5=0;S6=1; end
3 : begin S0=1;S1=1;S2=0;S3=1;S4=1;S5=0;S6=1; end
4 : begin S0=0;S1=1;S2=0;S3=1;S4=1;S5=1;S6=0; end
5 : begin S0=1;S1=1;S2=0;S3=1;S4=0;S5=1;S6=1; end
6 : begin S0=1;S1=1;S2=1;S3=1;S4=0;S5=1;S6=1; end
7 : begin S0=0;S1=1;S2=0;S3=0;S4=1;S5=0;S6=1; end
8 : begin S0=1;S1=1;S2=1;S3=1;S4=1;S5=1;S6=1; end
9 : begin S0=0;S1=1;S2=0;S3=1;S4=1;S5=1;S6=1; end
4'hA : begin S0=1;S1=1;S2=1;S3=1;S4=1;S5=0;S6=1; end
4'hB : begin S0=1;S1=1;S2=1;S3=1;S4=0;S5=1;S6=0; end
4'hC : begin S0=1;S1=0;S2=1;S3=0;S4=0;S5=1;S6=1; end
4'hD : begin S0=1;S1=1;S2=1;S3=1;S4=1;S5=0;S6=0; end
4'hE : begin S0=1;S1=0;S2=1;S3=1;S4=0;S5=1;S6=1; end
4'hF : begin S0=0;S1=0;S2=1;S3=1;S4=0;S5=1;S6=1; end
default: begin S0=0;S1=1;S2=0;S3=1;S4=1;S5=1;S6=1; end
endcase
end
endmodule