module test_counter;
parameter BITS=13, WORDS=251;
parameter pattern=24;
parameter clock_period=10;
reg [0:BITS] VMEM [0:WORDS];
reg timer,nclr,I0,I1,I2;
reg S0E,S1E,S2E,S3E,S4E,S5E,S6E;
reg [4:0] countseq;
wire S0,S1,S2,S3,S4,S5,S6;
reg [2:0] cycle;
integer i,j,s,c;
integer mon_out_file;
initial
begin
timer=1;
forever #(clock_period/2) timer=~timer;
end

//module under test
counter UUT (timer,nclr,I0,I1,I2,S0,S1,S2,S3,S4,S5,S6);
//generate clock waveforms

//read and write a file
initial
begin
mon_out_file=$fopen("mod.out");
$readmemb("test.vec",VMEM);
i=0;
{I2,I1,I0,nclr,cycle,S0E,S1E,S2E,S3E,S4E,S5E,S6E}=VMEM[0];
#clock_period;
for (j=1;j<=pattern;j=j+1)
begin
case ({I2,I1,I0})
3'd0 : countseq=5'd1;
3'd2 : countseq=5'd9;
3'd3 : countseq=5'd5;
3'd4 : countseq=5'd7;
3'd5 : countseq=5'd13;
3'd6 : countseq=5'd7;
3'd7 : countseq=5'd16;
default : countseq=5'd1;
endcase

for (c=1;c<=cycle;c=c+1)
begin
for (s=1;s<=countseq;s=s+1)
begin
if ((S0!=S0E)||(S1!=S1E)||(S2!=S2E)||(S3!=S3E)||(S4!=S4E)||(S5!=S5E)||(S6!=S6E))
begin
$fdisplay ($time,mon_out_file,"***Mismatch on input bitstream %b",VMEM[i]);
$fdisplay ($time,mon_out_file,"***AIN=%b%b%b, nclr=%b, cycle=%b, 7-segment=%b%b%b%b%b%b%b",I2,I1,I0,nclr,cycle,S0,S1,S2,S3,S4,S5,S6);
end
else
begin
$fdisplay ($time,mon_out_file,"***No mismatch on input bitstream %b",VMEM[i]);
$fdisplay ($time,mon_out_file,"***AIN=%b%b%b, nclr=%b, cycle=%b, 7-segment=%b%b%b%b%b%b%b",I2,I1,I0,nclr,cycle,S0,S1,S2,S3,S4,S5,S6);
end
$fdisplay (mon_out_file);
i=i+1;
{I2,I1,I0,nclr,cycle,S0E,S1E,S2E,S3E,S4E,S5E,S6E}=VMEM[i];
#clock_period;
end //for countseq loop
end // for cycle loop
end // for pattern loop
$fclose (mon_out_file);
end // initial

endmodule

module counter (timer,nclr,I0,I1,I2,S0,S1,S2,S3,S4,S5,S6) ;
//input
input timer ;
input nclr;
input I0,I1,I2;
//output
output S0 ;
output S1 ;
output S2 ;
output S3 ;
output S4 ;
output S5 ;
output S6 ;
// add your declarations here
reg S0,S1,S2,S3,S4,S5,S6;
reg [3:0] count_out;
reg [3:0] count1,count2,count3,count4;
//instantiations
//assignment
// add your code here
//generate the counting sequence according to input mode
//input 000 hold the counter at 5
//input 001 up from 1 to 9
//input 010 up from 3 to B every alternate
//input 011 up from 2 to E every alternate
//input 100 down from F to 3
//input 101 down from 9 to 1 every alternate
//input 110 down from C to 0 every alternate
//input 111 plain down counter

always @ (negedge nclr or negedge timer)
begin
if (nclr==0)
begin
count1=0;
count2=1;
count3=4'hB;
count4=4'hE;
end

else
begin
case ({I2,I1,I0})
0 : count_out=5;
1 : begin
if (count1==9) count1=0;
count1=count1+1;
count_out=count1;
end
2 : begin
if (count3==4'hB) count3=1;
count3=count3+2;
count_out=count3;
end
3: begin
if (count1==4'hE) count1=0;
count1=count1+2;
count_out=count1;
end
4 : begin
if (count1==3) count1=0;
count1=count1-1;
count_out=count1;
end
5 : begin
if (count3==1) count3=4'hB;
count3=count3-2;
count_out=count3;
end
6 : begin
if (count4==0) count4=4'hE;
count4=count4-2;
count_out=count4;
end
7 : begin
count1=count1-1;
count_out=count1;
end
endcase
end // if statement
end // always statement

//7-segment display
//
// S6__
//S5| |S4
// |_S3|
//S2| |S1
// |_S0|
//
always @ (count_out)
begin
case (count_out)
0 : begin S0=1;S1=1;S2=1;S3=0;S4=1;S5=1;S6=1; end
1 : begin S0=0;S1=1;S2=0;S3=0;S4=1;S5=0;S6=0; end
2 : begin S0=1;S1=0;S2=1;S3=1;S4=1;S5=0;S6=1; end
3 : begin S0=1;S1=1;S2=0;S3=1;S4=1;S5=0;S6=1; end
4 : begin S0=0;S1=1;S2=0;S3=1;S4=1;S5=1;S6=0; end
5 : begin S0=1;S1=1;S2=0;S3=1;S4=0;S5=1;S6=1; end
6 : begin S0=1;S1=1;S2=1;S3=1;S4=0;S5=1;S6=1; end
7 : begin S0=0;S1=1;S2=0;S3=0;S4=1;S5=0;S6=1; end
8 : begin S0=1;S1=1;S2=1;S3=1;S4=1;S5=1;S6=1; end
9 : begin S0=0;S1=1;S2=0;S3=1;S4=1;S5=1;S6=1; end
4'hA : begin S0=1;S1=1;S2=1;S3=1;S4=1;S5=0;S6=1; end
4'hB : begin S0=1;S1=1;S2=1;S3=1;S4=0;S5=1;S6=0; end
4'hC : begin S0=1;S1=0;S2=1;S3=0;S4=0;S5=1;S6=1; end
4'hD : begin S0=1;S1=1;S2=1;S3=1;S4=1;S5=0;S6=0; end
4'hE : begin S0=1;S1=0;S2=1;S3=1;S4=0;S5=1;S6=1; end
4'hF : begin S0=0;S1=0;S2=1;S3=1;S4=0;S5=1;S6=1; end
default: begin S0=0;S1=1;S2=0;S3=1;S4=1;S5=1;S6=1; end
endcase
end
endmodule