SPI DESIGN REPORT

Introduction

This document discusses the Serial Peripheral Interface (SPI ) design using Verilog HDL model. The design will be implemented it for XC4010XLPC84 chip, generate the bit-pattern configuration file, and use XS40 board to demonstrate the functionality. The SPI is a device that used for synchronized communication between the DSP controller and external peripherals or another controller. Typical applications include external I/O or peripheral expansion via devices such as shift registers, display drivers, and analog-to-digital (A/D) converters. The purpose of this design is to show and verify the two SPIs can be communicated to each other. One SPI operates as a master and one as a slave.

Operation

Figure A. shows how two SPIs can be connected for serial communication. The master provides the clock for synchronizing transmit and receive operations. When a byte of data is loaded into the master shift register (SPSHR_M), it initiates the transmission by supplying a slave select active-low (SS_). Data is exchanged between the master and slave shift registers in which the incoming bits are shifted into the master’s shift register, while the old values, are shifted out to the slave’s shift register. Since the master SPI initiates the transfer; therefore, if the slave SPI wanted to exchange information it must loaded data to its shift register (SPSHR_S) before the SS_ is driven low. As soon as the transmission is complete, data from each shift register is transferred to its corresponding SPDR (data buffer), and the SPI flag (SPIF) is set. The variable serial clock rate are listed below:

SPR1 and SPR0 – set serial clock (SCK) rate as follows:

SPR1&SPR0=00 SCK rate = sysclk rate /2

SPR1&SPR0=01 SCK rate = sysclk rate /4

SPR1&SPR0=10 SCK rate = sysclk rate /16

SPR1&SPR0=11 SCK rate = sysclk rate /32

where sysclk is the internal clock at which the MCU is running.

I/0 Pin Signals

Normally, the microcontroller unit (MCU) provides all the sufficient inputs signal to the SPIs to communicate with each other. However, for this design purpose we will manually force all the necessary inputs so that the desirable outputs can be observed. The input-output signals of the design are showed in the high level block diagram in Figure 1.

The top level IC design has the following inputs

RESET – global reset

SYSCLK – provided by internal IC signal (12MHz oscillator)

SPR1&SPR0 – control select serial clock (see above listed rate)

WDM – signal write data to the master’s shift register

RDM – signal read data from the master’s shift register to data buffer

IDM0-IDM7 – master parallel data input

WDS – signal write data to the slave’s shift register

RDS – signal read data from the slave’s shift register to data buffer

IDS0-IDS7 – slave parallel input data

The design produces the following outputs

SPIF – flag indicates transfer complete (LED)

S10-S16 –seven segment displays for the first four LSB of the master data buffer

S20-S26 –seven segment displays for the last four MSB of the master data buffer

SS10-SS16 –seven segment displays for the first four LSB of the slave data buffer

SS20-SS26 –seven segment displays for the last four MSB of the slave data buffer

The design is broken down into two main modules: master SPI and slave SPI. The I/O signals of the master SPI is showed in high level block diagram in Figure 2. The additional signals are used to interconnect to the slave SPI so that the two SPI are as follow:

MISO – serial input from slave SPI

SS_ - slave select transfer enable

SCK – transfer clock rate

MOSI – serial output to slave SPI

The ASM chart of the state machine of the master SPI is shown in Chart 1. The state machine consist of idle, setup, send_rec, and waiting states. When reset is asserted, the machine asynchronously enters idle state; bit_count is flushed with 0, SHSHR_M and SHDR_M are loaded with zeros, clear and SPIF is 0, and SS_ is 1. In idle state, if a positive edge of SCK occurs and WDM is asserted then the external parallel inputs will load new data to the SHSPR_M register. The machine will then enter setup state and checks to see if the WDM and RDM is deactivated. If the read and write is unasserted, the SPI will initialize the transfer by set SS_ to active low and starts the transfer at the next active edge of SCK and enters send_rec state. In send_rec state, the machine will increment the bit_count at the active edge of SCK and constantly check for nine cycles at every positive edge of SCK. If bit_count satisfies the condition, the machine will stop the transfer process, resets the bit_count to zero, asserts flag to indicate transmission is completed and enters the waiting state. The machine will wait for external signal to load the contents in the SPSHR_M to the read data buffer. The machine will repeat the cycle when the MCU is ready to write new data to the shift register.

The partial simulation result of master SPI is shown (see attachment) that the first value of MISO is sampled at the active edge of SCK when bit_count is 1; the last value of MISO is sampled at the active edge of SCK when bit_count is 8. Similarly, the MISO shifting takes action in the same bandwidth. Also, note that the slave select active range starts at the following active edge of SCK when WDM is unasserted and stops when the bit_count is 9. Moreover, the SPIF asserts simultaneously when SS_ is deactivated. SPIF only assigns to active for one clock cycle. When transmission is complete, the shift register holds the value and wait for RDM to assert. The data is store to the SPDR_M at the following active edge of SCK when RDM is asserted. By checking the MISO and MOSI serial value during the active-low of SS_, it showed that the master SPI is functionally correct.

The high level block of the slave SPI is shown in Figure 3. The interconnect I/O signals of the slave SPI are defined as follow:

SCK – serial transfer rate driven by master SPI

SS_ - slave select enable driven by master SPI

MISO – slave serial shift output

The slave finite state machine is shown in Chart 2. It is a simple state machine with idle and storedata states. The slave always anticipates for the SS_ active edge and ready to transfer data. Basically, slave SPI waits for SS_ signal in the idle state. If there is an active-low SS_, the slave SPI will simultaneously shifts and receives data for 8 clocks cycle as predetermined by the master. When transmission is complete and if RDS is asserted, the content of the slave shift register will be stored to the slave read data register and the machine returns to idle state and repeat the process.

The slave SPI partial simulation result is not shown. Since the slave SPI is dependent on the master control signal slave select enable, it is very difficult to show how the slave SPI behaves. We have run some simulation on the slave SPI module; however, it showed some very strange result so we decide not to include in this report to further misled the reader. Fortunately, we were able to run the overall design and the result showed that the master and slave SPIs are functionally correct (see attachment). The simulation printout showed that after the transmission is complete, whatever the content in the master shift register before the transmission is now appear in the slave’s shift register and vice versa.

The Verilog code for this design consist of two main modules, the master and slave modules as mention above, and other modules will be described as needed (see attachment). The top most module contains the instantiations of the two modules: master_spi5 and slave_spi1. The master_spi5 module consists of the instantiations of the clkmode and two gen4bit7seg (7-segment decoders). The clkmode module performs the selection of the serial clock depend on the control signals SPR0&SPR1. Following the instantiations are the two cyclic behaviors. The first one is the sequential behavior that controls the shifting mechanism. The second is the combinational behavior that describes the finite state transition. Similarly, the slave_spi1 module consists of two 7-segment instantiations and two cyclic behaviors that resemble the master_spi5 module with much less complexity.

IC Pin Assignment

The IC pin assignments are listed in random order so that it is convenience for connection (see attachment). There is no specific order for these pin assignments. The input pins are assume to be driven with +5V for logical 1 and 0V for logical 0.

Equipment List

1-XS40 board w/ XC4010XLPC84 FPGA chip

3-eight position dip switches

6- regular LEDs

4-seven segment LED displays

3-designer board

25- 4.7k resistors

8- 0.1uF capacitors

Hook up wires

Hardware Setup

The hardware consists of XS40 board with XC4010XLPC84 FPGA chip, 3 sets of 8 position dip switches that control the external signals, 6 regular LED, and 4 seven-segment LED displays for indicators. The dip switches are hook up with a 4.7k pull-up resistors and connect it to a +5V power supply. Moreover, eight VCC pins of the chip are also connected to the nominal +5V power supply and each pin is decoupled with a .1uF to Ground. Likewise, eight GND pins are also connected to Ground.

Procedure for Testing

Remove the XS Board apart from the design circuitry. Apply power to XS Board with a 9V DC wall transformer with a 2.1 mm female, center-positive plug through the jack J9 of the XS Board. Now download the bitstream to be tested. Once the bitstream is completely download, place the XS Board back into the circuitry and be careful not to disrupt the power to avoid repeating the process. Reminder that the XCS FPGA on the XS Board stores its configuration in an on-chip RAM which is erased whenever power is interrupted. Next, apply another +5V power supply to the circuitry. Start the test with the first set of eight switches in the on position. The other two sets of eight switches (without LED) are used to control the parallel bytes. These switched can be manipulated to either positions to indicate some specific byte to be transferred. Begin testing with a reset by turn off the switch #1, a red LED should be off. Now, turn on the reset switch and begin writing data to both SPI’s shift registers by turning off the switch #4 and #6, the two green LED should be off. Now the critical step is to turn on the slave write signal first, which is the switch #6 and then turn on the master SPI write signal, which is switch #4. At this moment, all the LEDs should be on and the transmission is taking place at the moment when the switch #4 is switch to the on position. Next, activate the read data by turning off the switch #5 and #7. The appropriate value should be displayed in the four sets of seven segment displays.

Cost Analysis

Note: The cost analysis excludes the XS40 board, the IC chip, and 3 designer boards. The approximate cost for all the equipment probably run about $150.

Summary

We are very pleased to see that the circuit is working. We decided not to further tempering the circuit to avoid the risk of ruining the working circuit. However, there are two things that could be adjusted to improve the circuitry/design. First, the four sets of seven segment LED displays need to be connected in series with a resistor for power dissipation. The 7-segment displays (right now) are set up without a resistor. It can withstand the heat dissipation through out the demonstration, but it will not last very long before it burns out. The other adjustment is the Verilog code. Right now the code is written to format all the signals with an active-high configuration but the dip switches are connected to have a logical 1 when it is in the off position. The code can be rewritten to have an active-low so that it can be consistent with the dip switches (on for logical 1 and off for logical 0). Furthermore, the SPIF’s indicator never turns on in this set up. Since the SCK runs in Megahert and the code is written to allow the SPIF signal to be asserted for only one clock cycle, the LED indicator probably de-assign its operation. The LED never blink to indicate the transmission is complete.