module SPI_TOP_LEVEL1
(
sysclk,reset,SPR0,SPR1,
IDM0,IDM1,IDM2,IDM3,IDM4,IDM5,IDM6,IDM7,
S10,S11,S12,S13,S14,S15,S16,
S20,S21,S22,S23,S24,S25,S26,SPIF,

WDM,RDM,RDS,WDS,
IDS0,IDS1,IDS2,IDS3,IDS4,IDS5,IDS6,IDS7,
SS10,SS11,SS12,SS13,SS14,SS15,SS16,
SS20,SS21,SS22,SS23,SS24,SS25,SS26
);
input sysclk,reset,SPR0,SPR1;
input IDM0,IDM1,IDM2,IDM3,IDM4,IDM5,IDM6,IDM7;

input WDM,RDM,RDS,WDS;
input IDS0,IDS1,IDS2,IDS3,IDS4,IDS5,IDS6,IDS7;

output S10,S11,S12,S13,S14,S15,S16;
output S20,S21,S22,S23,S24,S25,S26,SPIF;

output SS10,SS11,SS12,SS13,SS14,SS15,SS16;
output SS20,SS21,SS22,SS23,SS24,SS25,SS26;

// add your declarations here
//instantiations
master_spi5 M1
(sysclk,reset,SPR0,SPR1,
IDM0,IDM1,IDM2,IDM3,IDM4,IDM5,IDM6,IDM7,
S10,S11,S12,S13,S14,S15,S16,
S20,S21,S22,S23,S24,S25,S26,
SPIF,WDM,RDM,MISO,SS_,SCK,MOSI) ;

slave_spi1 M2
(reset,SCK,SS_,MOSI,RDS,WDS,
IDS0,IDS1,IDS2,IDS3,IDS4,IDS5,IDS6,IDS7,
SS10,SS11,SS12,SS13,SS14,SS15,SS16,
SS20,SS21,SS22,SS23,SS24,SS25,SS26,
MISO);
// add your code here

endmodule

module master_spi5
(sysclk,reset,SPR0,SPR1,
IDM0,IDM1,IDM2,IDM3,IDM4,IDM5,IDM6,IDM7,
S10,S11,S12,S13,S14,S15,S16,
S20,S21,S22,S23,S24,S25,S26,
SPIF,WDM,RDM,MISO,SS_,SCK,MOSI) ;
//inputs
input sysclk,reset ; //12MHz oscillator and reset signals
input SPR0,SPR1; //control signals to select clock rate
input IDM0,IDM1,IDM2,IDM3,IDM4,IDM5,IDM6,IDM7; //a byte data in
input WDM,RDM; //read and write signals
input MISO; //serial input received from slave SPI
//outputs
output SPIF; //flag indicates transfer complete
output S10,S11,S12,S13,S14,S15,S16; //first nipple to 7-segment LED
output S20,S21,S22,S23,S24,S25,S26; //second nipple to 7-segment LED
output SS_; //slave select, active low
output SCK; //selected rate for transfer
output MOSI; //serial transfer to slave SPI
//declarations
parameter all_zeros = 8'b0000_0000;
parameter idle = 2'b00;
parameter setup = 2'b01;
parameter send_rec = 2'b10;
parameter waiting = 2'b11;

reg [7:0] SPSHR_M; //a byte shift register
reg [7:0] SPDR_M; //read data buffer
reg [1:0] state,next_state; //FSM state
reg [3:0] bit_count; // 3 bit up counter
reg SS_;
reg SPIF;
reg clear; //reset the bit_count
reg MOSI;
//instantiations
gen4bit7seg G1 (SPDR_M[3:0],S10,S11,S12,S13,S14,S15,S16) ;
gen4bit7seg G2 (SPDR_M[7:4],S20,S21,S22,S23,S24,S25,S26) ;
clkmode G3 (sysclk,reset, SPR0, SPR1, SCK) ;
//assignments

//code
always @ (posedge SCK or posedge reset)
begin
if (reset==1) begin
SPSHR_M <= all_zeros;
SPDR_M <= all_zeros;
state <= idle;
MOSI<=0;
bit_count <=4'b0000;end
else begin
state <= next_state;
MOSI<=SPSHR_M[7];
if ((WDM==1) && (SS_==1)) SPSHR_M<={IDM0,IDM1,IDM2,IDM3,IDM4,IDM5,IDM6,IDM7};
if (clear==1) bit_count<=4'b0000;
else if (SS_==0) bit_count<=bit_count+1;
if (SS_==0) SPSHR_M<={SPSHR_M[6:0],MISO};
if ((RDM==1) && (SS_==1)) SPDR_M<=SPSHR_M;
end //else statement
end // always behavior

always @ (state or WDM or bit_count or RDM)
begin
clear <= 0;
SS_ <= 1;
SPIF <= 0;
case (state)
idle : if (WDM==1) next_state<=setup;
else next_state<=idle;

setup : if ((WDM==0)&&(RDM==0)) next_state<=send_rec;
else next_state<=setup;

send_rec : if (bit_count != 4'b1001)
begin SS_<=0; next_state<=send_rec; end
else begin SPIF<=1; clear<=1;SS_<=1; next_state<=waiting; end

waiting : if (RDM==1)
begin SPIF<=0; next_state<=idle; end
else next_state<=waiting;

default : next_state<=idle;
endcase
end //always behavior

endmodule

module gen4bit7seg (word4bit,S0,S1,S2,S3,S4,S5,S6) ;
//input
input [3:0] word4bit ;
//output
output S0,S1,S2,S3,S4,S5,S6;
// add your declarations here
reg S0,S1,S2,S3,S4,S5,S6;
// add your code here
//4 bits binary to 7-segment display
//
// S6__
//S5| |S4
// |_S3|
//S2| |S1
// |_S0|
//
always @ (word4bit)
begin
case (word4bit)
0 : begin S0=1;S1=1;S2=1;S3=0;S4=1;S5=1;S6=1; end
1 : begin S0=0;S1=1;S2=0;S3=0;S4=1;S5=0;S6=0; end
2 : begin S0=1;S1=0;S2=1;S3=1;S4=1;S5=0;S6=1; end
3 : begin S0=1;S1=1;S2=0;S3=1;S4=1;S5=0;S6=1; end
4 : begin S0=0;S1=1;S2=0;S3=1;S4=1;S5=1;S6=0; end
5 : begin S0=1;S1=1;S2=0;S3=1;S4=0;S5=1;S6=1; end
6 : begin S0=1;S1=1;S2=1;S3=1;S4=0;S5=1;S6=1; end
7 : begin S0=0;S1=1;S2=0;S3=0;S4=1;S5=0;S6=1; end
8 : begin S0=1;S1=1;S2=1;S3=1;S4=1;S5=1;S6=1; end
9 : begin S0=0;S1=1;S2=0;S3=1;S4=1;S5=1;S6=1; end
4'hA : begin S0=1;S1=1;S2=1;S3=1;S4=1;S5=0;S6=1; end
4'hB : begin S0=1;S1=1;S2=1;S3=1;S4=0;S5=1;S6=0; end
4'hC : begin S0=1;S1=0;S2=1;S3=0;S4=0;S5=1;S6=1; end
4'hD : begin S0=1;S1=1;S2=1;S3=1;S4=1;S5=0;S6=0; end
4'hE : begin S0=1;S1=0;S2=1;S3=1;S4=0;S5=1;S6=1; end
4'hF : begin S0=0;S1=0;S2=1;S3=1;S4=0;S5=1;S6=1; end
default: begin S0=0;S1=1;S2=0;S3=1;S4=1;S5=1;S6=1; end
endcase
end

endmodule

module clkmode (sysclk,reset, SPR0, SPR1, SCK) ;

input sysclk ;
input SPR0 ;
input SPR1 ;
input reset;
output SCK ;

// add your declarations here
reg [3:0] count ;
reg SCK;
// add your code here
always @ (posedge sysclk or posedge reset)
begin
if (reset==1) begin
count=0; SCK=0; end
else
case ({SPR1,SPR0})
0 : SCK=~SCK;
1 : if (count==0) begin
count=count+1; end
else if (count==1) begin
SCK=~SCK;
count=0; end
else count=count+1;
2 : if (count==0) begin
count=count+1; end
else if (count==7) begin
SCK=~SCK;
count=0; end
else count=count+1;
3 : if (count==0) begin
count=count+1; end
else if (count==15) begin
SCK=~SCK;
count=0; end
else count=count+1;
default : begin count=0; SCK=0; end
endcase
end
endmodule

module slave_spi1
(reset,SCK,SS_,MOSI,RDS,WDS,
IDS0,IDS1,IDS2,IDS3,IDS4,IDS5,IDS6,IDS7,
SS10,SS11,SS12,SS13,SS14,SS15,SS16,
SS20,SS21,SS22,SS23,SS24,SS25,SS26,
MISO);
//input
input reset; //reset the spi
input SCK; //clock rate generated by master spi
input SS_; //slave select enable from master spi
input MOSI; //serial input received from master spi
input RDS,WDS; //read and write signals
input IDS0,IDS1,IDS2,IDS3,IDS4,IDS5,IDS6,IDS7; //a byte data in
//output
output SS10,SS11,SS12,SS13,SS14,SS15,SS16; //first nipple to 7-segment LED
output SS20,SS21,SS22,SS23,SS24,SS25,SS26; //second nipple to 7-segment LED
output MISO; //serial transfer to master spi
// add your declarations here
parameter all_zeros = 8'b0000_0000;
parameter idle = 1'b0;
parameter storedata = 1'b1;

reg [7:0] SPSHR_S; //a byte shift register
reg [7:0] SPDR_S; //read data buffer
reg [1:0] state, next_state; //FSM state
reg MISO;

//instantiations
gen4bit7seg G1 (SPDR_S[3:0],SS10,SS11,SS12,SS13,SS14,SS15,SS16) ;
gen4bit7seg G2 (SPDR_S[7:4],SS20,SS21,SS22,SS23,SS24,SS25,SS26) ;
//assignments

// add your code here
always @ (posedge SCK or posedge reset)
begin
if (reset==1) begin
SPSHR_S <=all_zeros;
SPDR_S <=all_zeros;
state <=idle;
MISO <= 0; end
else begin
state <= next_state;
MISO <= SPSHR_S[7];
if ((WDS==1) && (SS_==1)) SPSHR_S <= {IDS0,IDS1,IDS2,IDS3,IDS4,IDS5,IDS6,IDS7};
if (SS_==0) SPSHR_S <= {SPSHR_S[6:0],MOSI};
if ((RDS==1) && (SS_==1)) SPDR_S <= SPSHR_S;
end //else statement
end //always block

always @ (state or SS_ or WDS or RDS)
begin
case (state)
idle: if (SS_==0) next_state <= storedata;
else next_state <= idle;

storedata: if (RDS==1) next_state <= idle;
else next_state <= storedata;

default: next_state <= idle;

endcase
end // always block

endmodule