Sachin Mohan

450 Oak Grove Dr. APT 307, Santa Clara, CA 95054

(408) 888 6052, (408) 216 7237

Email: sachinm@rocketmail.com


Objective: To obtain a challenging position in ASIC design and verification, to contribute to the organization's success and my self-development.

SUMMARY

SKILLS


Professional Experience


Staff Design Engineer


Architecture Definition of a memory bridge device for Cell phones

This memory bridge device is to replace the multiple memories required in the cellphone headsets with one SDRAM and one NAND Flash memory.

Working on architectural evaluation of a memory bridge device. Feasibility analysis for the numbers required by the marketing.


Verification of a Dual-Port SRAM

The 133MHz 18-Mbit DP SRAM is targeted towards high-end communication market e.g wireless base-stations.

Interfaced with the East-coast based design team to create verification plan for the full chip verification. Wrote PERL scripts to generate test vectors at the full chip level. Cross verification at the block level against behavioral models.


Behavioral modelling and Verification of TCAM4

Coded the behavioral model for the Ternary Content Addressable Memory (TCAM4). Interfaced with the verification team in India to verify the model against the customer spec.


Functional Characterization and Verification of 10G Framer

The chip was a Packet-Over-Sonet Framer (POSIC10G). Functional characterization of POSIC10G framer. Verification strategy and plan development for the POSIC10GVC part.




802.3 TBI interface Transactor Design - Motorola (01/02 – 04/02)

Design of a transactor for the verification of 802.3 specified TBI interface. This is an add-on module to allow the GMII transactors to connect to the ten-bit-interface of the DUT. It implements PCS and PMA layer functions of the PHY. It also incorporates an 8B/10B encoder and decoder modules. I was responsible for coding Rx Transactor BFM in verilog.


Verification Of a Reconfigurable Network Processor - Chameleon Systems (09/01 – 12/01)

Created test-plans and coded directed tests to verify the ‘tile’ block and random tests to verify concurrency.


Code Coverage Analysis - Nortel Networks (07/01 – 08/01)

Analyzed their test-suit from the viewpoint of code coverage and furnished recommendations to enhance the suit.


Verification Of a Reconfigurable Network Processor – Chameleon Systems (02/01 – 07/01)

Created test-plans and wrote tests to verify various modules of the chip, e.g. fabric, road-runner bus, code generator. Also did the code coverage analysis to optimize the test suit for better fault grading.




Design Of a CAN protocol implementation (11/00 – 01/01)

Conversion of a latch-based implementation of Controller Area Network (CAN) protocol to a flip-flop based implementation.


Design & Verification Of a microcontroller (10/99 – 10/00)

The Mcore based micro-controller was to be used in automotive Industry for anti-lock braking. Functional verification, Synthesize, Dynamic Timing analysis (timemill) and P&R of the Timer block.



VLSI Design Engineer


Design Of a 16 Bit RISC Processor (08/99 – 09/99)

Design, verify and synthesize the Program-Counter block.


Functional Verification of a 16 Bit RISC Processor (02/99 – 07/99)

Test-bench creation to apply the stimulus, Conversion from Compass-generated vectors to cycle-accurate Verilog vectors. Netlist to RTL conversion.


Redesign of 8-bit Microcontrollers for Sony Corp (04/98 – 02/99)

Migration of an 8-bit micro-controller from 1.4to 0.7technology, involving Schematic Entry, Test Bench Generation, Functional Verification and PNR.

Developed a software utility using Perl & Shell scripts to convert the stimulus file from ANDO-DIC 8031/32 format to a Verilog compatible format.




American Express Milleniax Conversion (10/97 – 03/98)

It involved converting the DB2 code to make it Y2K compliant.


Training in Software Development Process (07/97 – 09/97)

Project in C on UNIX to manage an employee database.




Advanced Chip Synthesis Workshop

The workshop was conducted by Synopsys Inc. at Motorola, Gurgaon. It focused on advanced chip synthesis methods.


VERA training

The workshop was conducted by Synopsys Inc. It focused on understanding the VERA language and its use to create verification environments.

sachinm@rocketmail.com ☎ (408)888-6052, (408)216-7237

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