Course Outline

1. Introduction to Microcomputer

   1. Microcomputer architecture and the system bus

   2. Von Neumann v Harvard architecture

   3. Program execution: CPU, ALU, Registers, Control Unit

2. Instruction Set Design/Architecture

   1. Single, multiple and general register design/machines

   2. Operations in instruction set

   3. Instruction type/size

   4. Operand types

   5. Instruction Format

   6. Addressing Modes

   7. Register design of 8/16/32 bit microprocessors

3. Processor Implementation Techniques

   1. Control Unit design, data and control path, Control Unit I/O signals

   2. Register types, user/special registers and their functions, data manipulation operations

   3. Multiplier/Divider implementation, co-processor unit, status/flag register

   4. ALU, Control and Command Register

   5. Hardwired/Micro programmed approaches to Control Unit design

   6. RTL Notation

   7. Control Unit Design Implementation

   8. Micro programmed Control Unit, Control ROM, micro program, sequencer

4. Memory

   1. Read/Write Cycle, Access Time, Wait States

   2. Memory v I/O Space, I/O Memory signal, Memory mapped v direct mapped devices

   3. Full/Partial address decoding scheme, implementations, merits/demerits

   4. Memory Interleaving, Memory Banks, Memory Bandwidth, SIMMs, DIMMs

5. I/O

   1. Peripheral devices, I/O interface chips, device/controller data transfer

   2. Data transfer through strobe signals, handshake signals, data transfer to multiple devices, GPIB 3-signal handshaking/protocol, device drivers

   3. Interrupts, interrupt based I/O, interrupt recognition mechanism

   4. ISR execution, return address, saving status flags, registers and processor state, vectored interrupts, auto-vectored interrupts

   5. Multiple interrupts, Non-maskable and maskable interrupts, 8259 interrupt controller

   6. EISA, VL and PCI Bus, PCI bus throughput, multiple master support, burst transfers, bus signal transmission, parameters defining bus performance

   7. Parallel Port, Port signals, Port registers/addresses, Parallel port timing, Interrupt/Polled operation, Parallel port operating modes

   8. Serial Port, Baud Rate, Asynchronous data transfer, frame, start, stop, parity bit, character size, sampling and synchronization, Synchronous data transfer, UART interface with system bus

6. Bus Arbitration

   1. Bus arbitration/contention, Parallel/Serial Scheme, Centralized/Distributed scheme, Fixed/Dynamic Priority

   2. DMAC Controller, DMAC configuration and initialization

   3. DMA page register, page boundary, transfer modes

7. Memory Hierarchy

   1. Principles of memory hierarchy, cache, principle of locality of reference, Cache organization, cache hit, cache miss

   2. Write through, write back, write around schemes, dirty bit

   3. Fully Associative, Direct Mapped, Set Associative scheme

   4. Bus Snooping

   5. Disk cache

8. Pipelining, Vector Machines, RISC Machines

   1. Pipelining, Pipeline throughput, machine cycles

   2. Pipeline Hazards: pipeline stalls, structural, data and control hazards

   3. Pipelining of functional units

   4. Vector Architecture, vector performance

   5. RISC Architecture, RISC performance

Text Books

1. David A. Patterson, John L. Hennessy, "Computer Architecture: A Quantitative Approach", Morgan Kaufmann Publishers, Inc.

2. William Stallings, "Computer Organization and Architecture", Macmillan