Resume Hosted by Evitan
Joseph Lee Turner
| Analytical Engineer with expertise in Computer and Digital Signal Processor (DSP) Architecture. Programming and Software Development skills, good Mathematical Abilities and a particular aptitude towards Logical Problem Solving. |
CAREER
| MOTOROLA GSM Cellular Infrastructure |
| TECHNICAL PROJECT MANAGER | Aug 96 - 99 |
 | Led team of the most complicated GSM CI digital circuit, Second Generation Generic Processor board, from prototype development through Software integration to production. |
| Currently leading design improvement program focusing on Manufacturability (DFM), Production Yield (FTY), Reliability (MTBF), and Material (DM) cost. |
| Technology includes MC68040/060 core, L2 Cache/Sync DRAM, co-processors for Token Ring/Ethernet LAN, LAPC/D TDM, serial and (VME style) MCAP interfaces. VHDL Antifuse, FPGA and PLD logic. Mixed 3.3V and 5.0V . |
| Instigated new design methodology with improved use of hierarchy and configuration control. |
| Recognised as UNIX technical expert. C, csh, sh (bourne), awk and MentorGraphics AMPLE languages. |
| Extensive travel to Chicago facilities in support of engineering activities. |
| Produced and maintained best-in-class project information web pages, with HTML and JAVA script, for company internal use. Wrote suite of UNIX applets to maximise department use of web browser with spreadsheets etc. . |
| DIGITAL DESIGN ENGINEER | Jul 94 - Jul 96 |
| Redesigned radio power control unit for DFM, FTY, MTBF. Key issues were highlighted by analysis of history and Accellerated Life Testing (ALT). Worked in team for a similar new radio product. |
| Extensive UNIX experience in data conversion. Worked closely with a group for data analysis in early stages of Statistical Process Control (SPC). |
| Developed design data (MentorGraphics) configuration and conversion program to feed engineering database, factory build, stock control and purchasing systems. |
| Troubleshooting on 16Mbps Token Ring LAN . |
THORN EMI SENSORS GROUP - 50 million turnover
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ELECTRONIC DESIGN AND DEVELOPMENT ENGINEER
| Sep 92 - Jul 94
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| Researched, designed and integrated a unique VME bus non-volatile data storage card for harsh-environment use on two avionic radar projects. |
| Worked closely as part of both project teams during integration stages. |
| Design technology included: (Altera MAX) EPLD VME slave interface with a two level interrupter, MC68302 embedded microcontroller, Flash E2PROM and autostore NVRAM. |
| Schematic capture entry and simulation using MentorGraphics v7/v8. EPLD design entry and simulation using MAX+PLUS2. |
| EPLD design using AHDL text description language. Microsequencer (SAM448) firmware design using ASM text description language. |
| FINAL YEAR PROJECT | Oct 91 - Apr 92 |
| Specified and designed a Data Flow interface ASIC, between a transputer and MP1 custom ASIC of a Mad-Postman Distributed Array Processor (DAP) network. |
| The interface used an Extended Token Store method of data synchronisation. |
| ASIC design capture using Solo 1400. |
| RUTHERFORD APPLETON LABORATORY (RAL) - SERC funded | |
| ELECTRONIC DESIGNER AND COMPUTER PROGRAMMER | Sep 90 - Sep 91 |
| University placement with European Incoherent Scatter Radar Group (EISCAT UK) in the Space Science Department. Researched into the mathematics of tracking the flow of high energy plasma in the ionosphere, using tristatic radar with a single active UHF transmitter. |
| Designed and constructed a dual-axis controller to direct the 32m parabolic antennas of an existing tristatic system (used previously for fixed position measurements). |
| Wrote and developed FORTRAN 77 software to give geographical representation of incoherent scatter data. |
| Working prototype included a T222 Inmos transputer, digital and analogue control circuitry. Firmware demonstrator written in OCCAM. Programmed logic with ABEL. |
| Received Associate membership to the University of Surrey for this period (AUS). |
| RECENT COURSES | ||
| UMTS - Motorola. | |
| Project Management - OPDC. | |
| Team Leadership workshop - Beaver. | |
| Comprehensive VHDL for ASIC design - DOULOS. | |
| MentorGraphics Idea Station - MentorGraphics | |
| Digital Cellular Systems - Motorola Training. | |
| Various Motorola business initiatives - Motorola Training. | |
| Includes: Competencies, Design For Manufacture (DFM), Take Back, Protecting Our Environment, Total Cycle Time Reduction. | ||
| UNIVERSITY OF SURREY | Oct 88 - Sep 92
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BEng (Hons) Electronic and Electrical Engineering
| Jun 92
| Chosen options in:
Digital Signal Processing, Computer Architecture, Machine Intelligence,
Control Systems, Telecommunications and Power Engineering.
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Diploma in Business Studies.
| Apr 91
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Project Planning (PERT), Accounts, Finance, Business Law, Teamwork.
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UNDERGRADUATE
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One GCE 'S' level and four GCE 'A' levels.
| Jun 88
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Two GCE 'AO', Five GCE 'O' and two CSE levels.
| 86 - 87
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| C, ALGOL 68, awk, sh (bourne), csh, MentorGraphics AMPLE, FORTRAN 77, OCCAM and various BASIC high level languages |
| 68000, Z80, 6800 and 8086 and low level languages |
| VHDL, Altera AHDL, ASM, PALASM and ABEL hardware description languages. |
| Experience of UNIX (SunOS, HP-UX), MSWindows, WindowsNT, NTX, DOS, Norsk Data SINTRAN iii and VMS systems. |
| SHERPA, CS/3, PROTOS, ACCESS and BATWINGS database systems. |
| Experience with a variety of logic analysers, analogue and digital oscilloscopes. |
| Most major word processing and spreadsheet packages. |
| Duke of Edinburgh bronze and silver awards; |
| Four years leadership position in uniformed youth group Campaigners. |
| Conversational Russian and French; recently traveled to China. |
| Date of Birth | | 7th March 1970 | |||
| Status | | Married with children | |||
| Mobility | | Full driving license and own car | |||
| Health | | Excellent, non-smoker | |||
| Location | | Swindon, Wiltshire, UK, SN25 | |||
| Telephone | |
available on request
| Email
|
evitan@bigfoot.com
| |
