Laboratory Experiments

1.0 JK Flip-flop

1.1    Place the 74LS76A JK flip-flop IC on the IDL800 Experimenter breadboard.

1.2    set the inputs PR = 1 and CLR = 0. Record the flip-flop outputs Q and Q. You should get Q= 0 and
        Q= 1. If you don't, check to see if you have assemble the IC correctly. (note: You must have your IC
        connected to Vcc and GROUND). Give a clock pulse to the CLK input of the JK flip-flop. Is there any
        changes at the Q and Q outputs? Why?

1.3    With Q still at zero, change input CLR to 1 and PR still set to 1. (Check to see that your Q is still at
         zero). Set J and K inputs as in the table below and record the Q (experiment) every time you set J
         and K to the appropriate logic values. Also, fill in the expected values for Q.
 

 
J
K
CLK
Q (expected)
Q (experiment)
0
0
1
1
0
1
0
1
 
 
 
 
            Is your Q (expected) and Q (experiment) the same? If they are not the same, double check to see if
         you had correctly obtained the expected Q values or you had assemble the IC incorrectly or your IC
         is faulty.
         Get your demonstrator's help if you have any problem.

1.4    Now set PR = 0 and CLR =1.
        What logic value do you get at the outputs Q and Q?
        Give a clock pulse to theCLK input of the JK flip-flops. Is there any changes at the Q and Q outputs?
        Why?
        Set J = 1 and K = 1 and followed by a clock pulse at the CLK input. Do you see any changes at the Q
        and Q outputs? Why?

1.5    Do you think that your JK flip-flop is functioning accordingly?
 
 

2.0 D Flip-flop

2.1    Place the 74LS74 JK flip-flop IC on the IDL80 Experimenter breadboard.

2.2    Set the inputs PR= 1 and CLR = 0. Record the flip-flop outputs Q and Q. You should get Q = 0 and
        Q = 1. If you don't, check to see if you have assemble the IC correctly. ( Note: You must have your
        IC connected to Vcc and GROUND).
        Give a clock pulse to the CLK input of the JK flip-flop. Is there any changes at the Q and Q outputs?
        Why?

2.3    With Q still at zero, cahnge input CLR to 1 and PR still set to 1. (Check to see that your Q is still at
        zero). Set D input as in the table below and record the Q (experiment) everytime you set D to the
        appropriate logic value. Also, fill in the expected values for Q.
 
 
 
 

D
CLK
Q (expected)
Q (experiment)
0
1
 
 
 
 
 
        Is your Q (expected) and Q (experiment) the same? If they are not the same, double check to see if
        you had correctly obtained the expected Q values or you had assemble the IC incorrectly or your
        IC is faulty.
        Get your Demonstrator's help if you have any problems.

2.4    Now set PR = 0 and CLR =1. What logic value do you get at the outputs Q and Q?
        Give a clock pulse to the CLK input of the JK flip-flop. Is there any changes at the Q and Q outputs?
        Why?
        Set D = 0 and followed by a clock pulse at the CLK input. Do you see any chandes at the Q and Q
        outputs? Why?

2.5    Do you think that your D flip-flop is functioning accordingly?
 
 

3.0  T Flip-flop
 

3.1    Place the 74LS76A JK flip-flop IC on the IDL800 Experimenter breadboard.

3.2    Construct a T flip-flop from the 74LS76A JK flip-flop.

3.3    Set the inputs PR=1 and CLR=0. Check the outputs Q and Q. They should be 1 and 0 respectively.

3.4    With Q still at zero, change CLR to 1 and PR still set to 1. (Check to see that your Q is still at zero).
         Set T input as in the table below and record the Q(experiment) every time you set T to the
         appropriate logic value. Also fill in the expected values for Q.

 
T
CLK
Q(expected)
Q(experiment)
0
1
 
 
            Is your Q(expected) and Q(experiment) the same ? If they are not the same, follow the tips
          suggested in 1.3 and 2.3.

3.5    Finally, do you think that your T flip-flop is functioning accordingly?
 

4.0 This part is optional

          If you still have time to work in the lab. Verify the waveform in Figure 9 below. Use the 74LS76A JK
          flip-flop to represent the JK flip-flop inputs in the diagram.