1.0 Basic gates
1.1 Place the 7404 NOT gate on the experimenter breadboard. Connect pin 7 (GND pin) to grpund and pin 14 (Vcc pin) to +5V supply of the experiment.
1.2 Apply all the input combination to the input pin of the 7404 IC. Refer to the truth table in the prelab exercises. Use the input that you have assigned in the pre lab exercises.
(Note: Apply only one input combination (if the gate has more than one input) at a time. You will use the switches on the experimenter as inputs to the ICs. An 'ON' switch on the experimenter will give a logic 1 and on 'OF' switch will produce a logic 0. The outputs from the ICs will be connected to the LEDs on the experimenter. A logic 1 output will light up the LED on the experimenter while a logic 0 will OFF the LED. Refer to the Appendix for some useful tips and guidelines for hardware experiments).
1.3 Verify the truth table for the gates. Record your observation in the logbook.
1.4 Is this IC functioning correctly?
1.5
Repeat procedure 1.1 to 1.4 for the following gates:
OR. AND, NAND, NOR and EXOR.
1.6 Assemble the circuit as in FIGURE 1.12 in the prelab exercises. Remember to connect the Vcc and GND pins appropriately. Use the pin assignments that have been made in the prelab exercises.
1.7
Apply all the input combinations and verify your output with reference
to the truth table in 4(a) of the prelab exrecises. Record your observations
in the log book.
2.0 Combinational logic.
2.1 Assemble the circuit in FIGURE 1.10. Use the pin assignment that you have made in the prelab exercise. Remember to correctly connect the Vcc and GND pins for every IC in use.
2.2 Apply all the input combinations and verify its output with reference to the truth table. Record all your observations in the log book.
2.3 If there is any unmatched result, troubleshoot your circuit. Get your lab demonstrator's help if you have any problem.
2.4 If your circuit is functioning accordingly, demonstrate your circuit, to the lab demonstrator and get his/her approval that your circuit is working.
2.5
Repeat procedure 2.1 and 2.4 for the combinational circuit in FIGURE 1.11.
There is no report for this experiment.