Subtraction Using 4 bit 74LS83 Full Adder IC
 
FIGURE 6    Parallel adder used to perform subtraction (A-B) using 2's complement system. The bits of the subtrahend (B) are inverted , and C0 = 1 to produce 2's complement.
 

FIGURE 6 shows how subtraction between two numbers that is A-B can be performed using 74LS83 4 bit Full Adder. Here the number for B (subtrahend) is represented in 2's complement form. This is obtained by inverting each bit of the subtrahend and adding 1 to the LSB. The process of adding 1 to the LSB of the subtrahend is accomplished by setting C0=1.
For example, if we want to perform the subtraction of 6-4.
Therefore, the inputs A3-A0 are represented by 0110 and the inputs B3-B0 will be represented by the inverted of 4 that are 1011. The subtraction is done as shown below which is actually addition in 2's complement.
 
 

The outputs S3 to S1 represent the results of the subtraction operation. S3 is the sign bit of the result and indicates whether the results is + or -. The carry output C4 is disregarded.
 
 
OBJECTIVES | DISCUSSION | PRE LAB | PROCEDURE | RESULTS