Design a synchronous sequntial system thet will give an output of one if and only if the input x is zero and immediately previous to that an even number of "10" sequences are completed (no overlapping allowed).
Otherwise the output is zero.
An RST input is also available to reset the system and put it in its initial
condition with Z=0. Implement the circuit using T flip-flops with minimum
number of flip-flops and gates.