DISCUSSIONS

Clocked Flip-flops

There are several types of clocked Flip-flops that are used in a wide range of applications.

1. SR flip-flop
2. JK flip-flop
3. D flip-flop
4. T flip-flop
 

First, we will describe the principle ideas that are common to all of them.

Clocked Flip-flops have a clock input that is labeled CLK, CK or CP. In most clocked Flip-flops, the CLK input is edge-triggered, which means that it is activated by a signal transition. This is indicated by the presence of a small traingle on the CLK input as shown in Figure 1.
 

 
 

Figure1: Clocked Flip-flops have a clock input (CLK) that is active on either a)Positive-edge or b)Negative-edge.

 
 
 

The control inputs determine the effect of the active clock transition.

The clock can be of two types which are the positive-edge triggered or the negative-edge triggered.

Clocked flip-flops also have one or more synchronous control inputs depending on the type of flip-flops.
 
 

Flip-flop types
Control inputs
SR flip-flop 
JK flip-flop 
D flip-flop 
T flip-flop
S and R 
J and K 
T
 

These inputs are named synchronous because they will only affect the Flip-flop outputs during the active clock transition (positive or negative edge).
All flip-flop have two outputs called Q and it's complement, Q*.
 

Clocked SR Flip-flop.

Figure 2 shows the logic symbol for a clocked SR flip-flop that is triggered by the positive edge of the clock signal.
The S and R inputs control the state of the flip-flops in the manner as shown in the truth table in Table 1.
 
 
 

   Figure 2: Clocked SR flip-flop that responds only to the positive-going edge of a clock pulse.
 
 
 
**NA = Not Available
Table 1: SR Flip-flop Truth Table.
 
 
Inputs 
S          R         CLK
Outputs 
Q
       0           0           ^ 
       0           1           ^ 
       1           0           ^ 
       1           1           ^
Qo 
Ambigous
Table 2: Summary of the SR truth table in Table 1.
 
 
 

Clocked JK Flip-flop
 

 
 
Figure 3: JK flip-flop that triggers only on negative-going transitions
 

One example of edge-triggered clocked JK Flip-flops available in the TTL 74-series IC is 74LS76A. The JK flip-flops here are of the negative-edge triggered. The 74LS76A JK Flip-flops also have two asynchronous inputs called PRESET (PR) and CLEAR (CLR) as shown in Figure 4.
 

 
 
 
Figure 4: Clocked JK Flip-flops with asynchronous inputs - PRESET (OR) and CLEAR (CLR)

 

PRESET
CLEAR
FF response
0
Clocked operation 
Q = 1 
Q = 0 
Not used
Table 3: Truth table for the asynchronous inputs response
 

They are asynchronous inputs because they operate independently of the synchronous inputs and clock input. These asynchronous inputs can be used to set the Flip-flop output to the 1 state or clear the Flip-flop output to the 0 state at any time, regardless of the conditions at the other inputs. Stated in another way, the asynchronous inputs are override inputs which can be used to override all other inputs in order to placethe FF in one state or the other. The PRESET and CLEAR inputs are active-low inputs as indicated by the bubbles on the Flip-flop symbol.
 

Clocked D Flip-flop
 
 

 
 
Figure 5: Clocked Positive Edge Trigered D Flip-flop.

 
One example of edge-triggered clocked D Flip-flop available in the TTL 74-series IC is 74LS74. The D Flip-flop here are of the positive-edge triggered. The 74LS74 D Flip-flops also have two asynchronous inputs called PRESET (PR) and CLEAR (CLR) as shown in Figure 6.
 
 
 

 
 
  Figure 6: Clocked D Flip-flop with asynchronous inputs - PRESET (PR) and CLEAR (CLR)

 
 
 

The asynchronous inputs here are also active-low inputs and function the same way as for the 74LS76A JK flip-flops as in Table 3.
 

Clocked T Flip-flop
 
 

 
Figure 7: Negative-Edge Triggered Clocked T Flip-flop

Clocked T-Flip-flop is not available as a stand-alone TTL device. However, you can construct a Flip-flop from the JK flip-flops such as the JK Flip-flop from the 74LS76A IC by tying together the J and K inputs as shown in Figure 8.
 

 
Figure 8: T Flip-flop from JK Flip-flop.