#technology ideal18u
	// we specify what kind of technology we use
	// ideal18u means 18 microns technology with constant gate delays
	// most technologies should define behaviour for :
	// uclock(period)
	// ureset(time1,time2,...)
	// not()
	// and(), nand(), or(), nor(), xor()
	// bufif()
	// *** i'm not sure whether it should be case-sensitive or not
	// *** an idea is: it is case-sensitive but you may not define
	// *** tho identifiers like "add" and "aDD"
#include "someother.glh"
	// includes another glh

connect(list_a, list_b)
	// all functions create modules and return references to them
	// somewhat like constructors, modules get a type when constructed
	// and utility functions can be called on them

	// utility functions would look something like connect.dosomething(...) { ... }

	// all local variables of the functions become members of the module
	// that is: local variables are persistent

	// you can use detach(variable) to destroy the link between a variable
	// and the value it references, however note that detach(some_module)
	// will have no effect whatsoever on the module itself, all wires remain
	// connected exactly as they were, however the module cannot be referenced
	// anymore through that particular name

	// calling detach() on something that does not exist doesn't generate
	// an error
	// all function paramaters are automatically detached before assigning
	// them new values when calling a function; they may also be detached
	// at the end of the function

	// there are no type definitions mainly because there are very few types
	// a variable can be an integer, string, wire, list or another module
	// however you can check the type of a variable that has been passed to
	// you as a parameter using: isinteger(), isstring(), isatom() integer or string
	// iswire(), ismodule(), isany() check if the identifier actually exists,
	// isnull() just the opposite

	// a list may contain integers, strings, references to wires and modules
	// at the moment there is no particular purpose for a list to contain other
	// lists and as a result it is not allowed
	// *** I'm afraid that making the language too powerfull might allow
	// *** odd things to be done (like obfuscated C)
	// an element may appear more than once in a list
	// you may define lists like this [1, 2, 'ab', wire1, module1, 1..(i+2), 7..0]
	// concatenation of lists using + sign is allowed, comparison of lists
	// a[list] expands to: [a.elem1, a.elem2, a.elem3 ...]
	// potentially powerfull: a[1,2,3]+a.b[1,2]=[a.1,a.2,a.3,a.b.1,a.b.2];
	// notice that giving this value to a list creates the structures a and a.b
	// as members in the current module, and the list is passed as a list of
	// references to these variables
	// if you intend to pass a list of names, try ["a.1","a.2"]
	// example:
	//	flags=["carry","halfcarry","overflow","zero"];
	//	connect(a[flags],b[flags]);

	// the language generates a tree of modules and submodules
	// each call to a constructor generates a new node in the tree
	// with a name of $xxxxxxxx which cannot be referenced directly
	// as valid identifiers do not begin with $
	// if you want to use that module someother time you should pass the
	// reference given by the constructor to another variable

	// on certain ocasions you might not need to do this as all wires were
	// connected when the module was instantiated
	// as in: b=and(a[1],a[2]).out;

	// the equal sign "=" has special meaning depending on the types of left and
	// right operands
	// undefined = integer, string or list
	//	exactly what you would expect in a normal C program
	//	note that a=b=c is not allowed
	// variable with integer, string or list value = any of integer, string or list
	// 	just changes the value of the variable
	//	if it was integer before, it doesn't mean it can't become string
	//	or vice-versa
	// undefined = wire or module
	//	associates the particular wire or module with the new name
	// wire = wire
	// 	connect the two wires togheter
	//	notice that it doesn't matter wich one is the input and wich one is the output
	// module = module
	// the two modules become one, and can be referenced by either name
	// !!! very dangerous
	// possible pitfall: if A and B are two modules containing some wires with the
	//    same name and C is a module containing only those wires, the idea of
	//    conecting the modules like A=C; B=C; might occur to you
	//    however the result will be that A,B and C will all be mixed up together
	//    possible use A.in1=somewire; A=somemodule();

	// function !!!/constructor .create

	// possible pitfalls
	//	list_of_wires=list_of_wires  does NOT connect wires together

{
	assert(islist(list_a),"failure in connect - first parameter is not a list");
	assert(islist(list_b),"failure in connect - second parameter is not a list");
	q=uniquename();
	// a random generated unique name of string type
	j=0; k=0;
	foreach (list_a,i)
	// i takes all values in list_a, in the precise order given by the list
	// same as with the equal sign
	// a detach(i) is done prior to each assignment by default
	// otherwise all wires would be bound toghether and this is not what
	// we want
	{
		this[q][j]=i;
		j++;
	}
	foreach (list_b,i)
	// *** any suggestions what to replace the "in" with
	// *** it's very much C-unlike
	{
		this[q][k]=i;
		k++;
	}
	assert(j==k,"failure in connect - list sizes do not match");
	// *** not sure whether it should be assert or assume
}

main()
{
	foreach ([0..7],i) pad(ext_wire[i]);
		// lists are in brackets
	connect(out[0..7], stage_two[6..0,7]);

	out1.0=and(ext_wire.1,ext_wire.2,ext_wire.3).out;
		// standard gates accept variable number of inputs

	out1.1=nand(ext_wire[1..5]);
		// ext_wire[1..5] expands to [ext_wire.1, ext_wire.2, ext_wire.3 ...]

}

// just added
// $$global variable
// structures defined by technology

// and(), or() ...
// any parameters become wires 1,2,3... in this order
// lists are expanded

// flipflop
// any parameters become wires in this order:
// d, clk, en, q, qn,
// set, reset, syncset, syncreset,
// set_n, reset_n, syncset_n, syncreset_n
// wires can be assigned afterwards
// wires not assigned do not provide the specific functionality

// vlog_adder(bitcount)
// a[],b[],cyin,out[],cyout

// vlog_mux(bitcount)
// in[],out

// .finalize for all modules
// cannot interact with already finalized modules

// connect