QUANG
PHUNG
3301
Etoile Court
(408)
274-5301 (Home & Message)
(408)
981-4196 (Cell)
http://geocities.datacellar.net/quang_phung/
JOB OBJECTIVE: Seeking
a position in ASIC / FPGA design and verification.
EXPERIENCES:
· Twelve
years of experience in hardware design.
· Ten
years of ASIC / FPGA design.
· Knowledgeable
of ASIC / FPGA design tools: Verilog, Synopsys, Xilinx FPGA, Axis hardware
accelerator.
· Familiar
with several networking interface protocols AnyPhy, PosPhy, Utopia.
· Familiar
with several memory interfaces SRAM, DDR DRAM.
· Knowledgeable
of MPEG I-II for VCD / DVD application.
WORK HISTORY:
01/2000 - Present: Hardware Engineer, Cisco Systems, Inc., San Jose, CA
· Co-designed
a Virtex II Xilinx FPGA for Any Service Any Port (ASAP) line cards of Cisco
Multi Services Switch product – MPSM-OC3:
Designed a Master AnyPhy 2 (AP2) Interface to 2 Freedm Frame
Relay framers and 1 IMA ATM framer.
Designed a Master PosPhy 3 (PL3) Interface to 12xJET framer.
Designed an Ingress Controller to transfer Ingress packets from AP2
(Freedm’s and IMA) and PL3 (12xJET) interfaces to Wintegra Network Processors.
Designed a format converter to convert Ingress packets into Wintegra required
packets.
Designed an Egress Controller to transfer Egress packets from Wintegra
Network Processors to Freedm’s, IMA, and 12xJET framers. The Egress Controller
has to poll up to 2K ports and transfer packets according to each individual
port rate to its corresponding framer such that no traffic underrun detected by
the framers. Designed a format converter to re-convert Wintegra formatted
packets back into individual framer packets.
Wrote unit testbench to verify the design.
Debugged the FPGA design at board level using logic analyzer.
· Worked
on the MPLS option of the OC192 ASIC ATM switch:
Designed Frame Count Controller module that consists of
SRAM-based Link List Controller sub-module as well as other supported
sub-modules.
· A member
of the ASIC OC192 ATM switch chip set team:
Maintained and enhanced DDR SDRAM Interface Controller of Mercury chip.
Maintained and enhanced Con ID Lookup module (interfaced to Cisco CAM2)
of Talos chip.
Designed trace RAM’s to help debugging Mercury chip.
Maintained and enhanced Memory Test Engine module for Talos, Hercules,
Mercury, and Europa of the OC192 ASIC ATM switch chip set.
06/1997 – 01/2000: Staff Engineer, Sony Electronics, Inc.,
San Jose, CA
· Worked
on the 4th & 5th Generation Sony DVD players:
Set up the verification environment on Synopsys Eagle, and Axis
hardware accelerator.
Modified existing internal bus controller module to add additional
channels.
· Successfully
brought Sony ASIC DVD decoder CXD1930 to mass production for 3rd
Generation Sony DVD players in the worldwide market:
Worked with system engineers to integrate the DVD ASIC and Host CPU
into the system board.
Performed system debugging, testing.
· MPEG II
decoder for DVD - second spin: modified Host Interface Unit to meet new
requirements for DVD application, modified the DMA Interface Controller to
support interleaving between 2 DMA channels.
· DVD
demux for VCD: verified current DVD demux to support VCD application.
· Timing
analysis using Motive.
09/1995 – 06/1997: Senior Design Engineer, Sony Electronics, Inc., San Jose, CA
· MPEG II
decoder for DVD - first spin: set-up simulation/synthesis environment for
Verilog/Synopsys, designed Host Interface Unit to interface Motorola/Hitachi SH
CPU’s with the MPEG II decoder, designed the DMA Interface Controller to
interface with Motorola/Hitachi SH DMA Controllers, wrote the Verilog
behavioral model for Motorola/Hitachi SH CPU’s read/write bus cycles, debugged
chip on the system.
12/1991 – 09/1995: Senior Design Engineer, Hitachi Micro Systems, Inc., San Jose, CA
· MPEG II
decoder for set top box: set-up simulation/synthesis/test environment for
Verilog/Synopsys/Compass, designed Host Interface Unit to interface
Motorola/Hitachi SH CPU’s with the MPEG II decoder, designed a pipelined 8-bit
multiplier.
· Hornet
(ASIC Micon): Established the design environment for ASIC Micon (ASIC & CPU
on the chip), wrote a bus timing model for the CPU core, ran Mentor Quicksim v8
simulation, cross-checked with Verilog simulation and Synopsys, used Compass
for floorplanning and layout, ran LVS verification using Cadence - Dracula.
· IKAP -
MROM (8/16-bit microcontroller): Replaced EPROM in the chip by mask ROM
version, redesigned the interface logic for mask ROM using Mentor Quicksim v7,
floorplanned and worked with layout designers using Cadence - Tancell, ran LVS
verification using Cadence - Dracula, characterized the device on tester and
bench, prepared document for QA mass production approval.
· IKAP -
EPROM (8/16-bit microcontroller): Designed I/O interface logic for I/O pins
using Mentor Quicksim v7, floorplanned and worked with layout designers using
Cadence - Tancell, ran LVS verification using Cadence - Dracula, wrote assembly
programs to test the chip, generated test patterns, designed bench test board,
characterized the device on bench, prepared document for QA mass production
approval.
09/1990 – 12/1991: Design Engineer, T-Com Corp., Mountain
View, CA
· Option 3
board: Designed SLC96 datalink, fractional T1 transmitter/receiver, and UDC
transmitter/receiver cards as options for the T1 Transmission Analyzer 235A
using Xilinx FPGA 3000 family.
· T1
Transmission Analyzer 235A: Converted discrete logic for T1 Transmitter and
Receiver cards to Xilinx FPGA 3000 family, modified the design to meet Xilinx
FPGA requirements, worked with programmers to debug and generate software for
the instrument.
07/1989 – 09/1990: Design Engineer, Toppan, Santa Clara,
CA
· NPU
(Network Processing Unit): member of a team that was responsible for shrinking
the design from 1.3 to 1.0 um CMOS, captured schematics, built macro cells,
floorplanned and worked with layout designers, ran DRC, ERC, and LVS
verifications.
· Designed
several CMOS AC/ACT gates such as nand, nor, xnor, xor, counters, registers,
etc. Ran SPICE simulation.
01/1988 – 07/1989: Test Development Engineer, Teledyne, Mountain View, CA
· Designed
test boards and wrote test programs using Turbo Pascal to test several analog
products such as: op-amps, A/D's, voltage regulators on the ICTS tester.
SKILLS: Proficient
in Verilog.
ASIC/FPGA design tools, Synopsys, Cadence.
Familiar with C, Unix (Sun, HP), Linux,
Windows.
Perl, Tcl/tk.
EDUCATION:
BSEE at UC
Berkeley, 12/1987.
MSEE at Santa Clara University, 03/1997.
TECHNICAL ACHIEVEMENTS:
· Patent
holder of US
Patent No. 5,916,312.
· Two
pending patents related to Host Interface Unit, one pending patent related to
Polling Algorithm in networking.