Today's VLSI technology allows us to construct large, complex systems with million transistors on a single chip. Most of the existing high level synthesis systems give more priority to optimization of area, power, re- source and time steps compared to interconnection cost, whereas the later becomes predominant with the technology scaling and increase in complexity. Further, field programmable gate arrays (FPGA) are now becoming attractive platform for prototyping. Programmable devices tend to have limited wiring resources between the data path elements. This work is concerned with the development of a CAD tool for HLS named, "Structured Architecture Synthesis Tool (SAST)", which incorporates structured architecture generation with special emphasis on optimization of interconnect area. The too takes a behavioral description written in 3-address form and generates synthesizable RTL codes with scripts for compliance with standard design tools like Synopsys, Magma etc.