VHDL Module Generator

VERSION 1.10

An EDA tool for VHDL design entry that provides a rapid-prototyping design environment by overcoming current weaknesses in VHDL design entry, facilitating reusability of hardware modules and enabling seamless design hierarchy manipulation through a graphical rich and user-friendly user interface.

Presented by:
Microelectronics and Computer Engineering Department (MiCE)
Faculty of Electrical Engineering
Universiti Teknologi Malaysia

Snap Shot

Download installation: setup.zip (Installation package includes user manual and tutorial) (Updated on 10-04-2002)

Download user manual: VHDLMG.pdf

Getting started: See tutorial (Updated on 20-01-2000)

For further information, enquiry, comment, etc., please mailto koaykh@tm.net.my

You are visitor no. since 19 January 2000.

Prepared by Koay Kah Hoe
Last modified: 10 April 2002