1. Technical skills
2. Work Experience
3. Projects Completed
4. Education

Technical Skills   

Applications	Gigabit Ethernet, Fast Ethernet, IEEE 802.3, ATM, ATM forum’s Traffic Management Specification, Motorola DSP 56800 architecture, ARM architecture, SoC design with System-C, Nortel Passport 8600 Enterprise Ethernet Switch
Languages	VHDL, Verilog, C, Assembly, Perl
CAE Tools	Synopsys DC and FPGA tools, MTI, Verilog-XL, DeBussy debugger, Exemplar Logic, Xilinx FPGA synthesis tools, Active State (state machine) Editor
Operating Systems	UNIX, MS-Windows

Professional Experience

i. Working as Consultant with ZaiQ Technologies Inc, since Jan 2000 till date. 

   Consulted for CoWare Inc, Santa Clara, CA

   Nortel Networks, Santa Clara, CA.

ii. Woked as Design Engineer with Motorola India Ltd, since April 99 to Dec 99. 
   (company info at http://geocities.datacellar.net/rajatmr/www.mot.com)

iii. Worked as Design Engineer with CG-CoreEl Logic Systems Ltd., since
     July 97 till April 99. (company info at http://geocities.datacellar.net/rajatmr/www.coree.com)

Projects Undertaken
10/100Mbps Ethernet NIC

Description         : Design and implement 10/100 Mbps Ethernet NIC to evaluate the MAC core in live network. The MAC with glue logic is implemented to get a complete DLL layer functionality on two Xilinx FPGAs.
Duration             : 10 months
Team Size          : 2
Responsibilities : Been through entire life cycle of the project.

• Understand the MAC layer functionality as detailed in IEEE 802.3u standards

• Developed the specification and detailed RTL design document for the memory management interface, physical layer interface, ISA interface, synchronization circuit and TX controllers
• Write Synthesizable RTL code for all the above blocks
• Implemented the entire design in two Xilinx FPGAs, each with gate count of 28k, at 50MHz
• Resolve the timing issues by suitably constraining systhesis and place and route processes.
• Performe post layout timing simulation for entire design

• Planned a strategy to test all the MAC features
• Prepared the layout of Physical Interface using a dedicated Physical Layer device (SEEQ)
• Schematic and routing of 4 layerd PCB for ISA addon card
• Coded a preliminary C program for testing NIC functionality in DOS mode

Detailed info at 10/100Mbps Ethernet NIC

Ethernet NIC MII/RMII interface adapter card
Description      : Design and fabricate a addon card for MII/RMII interface card for 10/100 Mbps NIC
Duration          : 2 months
Team Size       : 2
Responsibilities :

• Understand the RMII/MII interfaces
• Integrate MII/RMII interface between MAC and phy device.
• Synthesis and routing of additional logic with MAC
• Logic optimization to meet timing and area issues
• Designed schematic and routing for the addon card
• Testing of the NIC in live network
• Full duplex mode of operation with autonegotiation

Test Bench for ATM Traffic Policer
Description      : Test the functionality of the Policer Core cell for all types of connections supported by it.
Duration          : 2 months
Team Size       : 1
Responsibilities :

• Understanding of ATM forum's traffic management specifications
• Designed and coded a behavioral test bench to test the functionality of policer as used with ATM switch
• Implemented the generic flow control algorithm at a higher level of abstraction

Education Details

Bachelor of Engineering in Electronics & Electrical Communication from PEC, Chandigarh. Passed out in June 1997 and secured 72% marks.

Received the silver medal in B.E., for best Major Project.