Work Experience:
Siemens ICT currently Exalt-Technologies Ltd.Rammalla,
Senior FPGA Design Engineer.
·
Responsible
for training new hardware and FPGA engineers and students
·
Hardware
board and FPGA designer for Next Generation SDH equipment. Responsible
for the CPU and management part of the board and the SDH APS protocol design
and implementation on FPGA
·
FPGA
design of Telecom equipment based on SONET/SDH technology. Responsible for
design and implementation of parts of the SDH protocol
·
Board
and FPGA design of a Telecom device based on ATM, E1/T1, SONET/SDH &
Ethernet technologies. The work includes system, board, algorithm and
protocol design and ATM protocol implementation on FPGA. Responsible for AAL5
protocol design on FPGA and the integration of external cores
·
Software
design of ATM/POS chip driver and testing. Responsible for the Embedded
OS kernel design, driver spec definition and system test software
Siemens Data
Communication Ltd,
Karmail, Israel, 1998 – 1999
·
Board
design of Gigabit Ethernet Switches. Responsible for designing the
switching core and the interfacing to the management part over PCI bus
·
Training
on the hardware board design and data communication
Arab Turnkey Systems (ATS.) Ramalla,
Design
of software that connects between Oracle database and Java. The
training included building some small applications that run over web and local
LAN
Independent projects (1996-2005)
-
Phone
index software book. First release was based on Visual Basic and MS-access,
second release was based on Java and Oracle 8i database
-
Tailors
shop custom software based on Visual Basic and MS-access
-
Several
OpenSource free hardware cores such as floating point unit, Bluetooth, ISDN,
TDM and HDLC
Education:
M.Sc. of Technology and Innovation Management,
Attended some courses of MBA program at
B.Sc., Major: Electrical Engineering,
Minor: Computer Science,
Hardware and software skills:
·
Programming/Hardware Description
Languages: VHDL, C, Assembly,
Visual Basic, Java, HTML and basics of Verilog HDL and SQL
·
TeleCom & DataCom protocols: ATM, Fast & Gigabit Ethernet, TCP/IP, SONET/SDH,
E1/T1,TDM, ISDN, HDLC and Bluetooth
·
Hardware design tools: Modelsim, Leonardo, Altera Quartus, Xilinx webpack and
Mentor Graphics Design Architect
·
Hardware
technologies: Altera’s APEX & ACEX and Xilinx’s Vertix devices
·
FPGA & HDL design: Ethernet, ATM, TDM, ISDN, HDLC, Bluetooth, processor,
FPU, memory cores hardware design
·
Good
knowledge in PCI bus design and interface
Relevant Experience and areas of
interests:
·
MSc. Thesis:
"Free Open Source as a Technology Transfer
tool for the Arab world"
·
MSc. Graduation Project: Analysis and study the topic 'Driving
Innovation through Research & Design incubation'
·
BSc. Graduation Project: 'A complete set of PC based Measurement Tools' Full design of the
Conditioning, Digital circuits, DSP, PC Interfacing and software drivers
·
Computer seminar
entitled: Games, Multimedia and graphics software design
·
Current Research: Run-Time reconfigurable logic applications and related
tools
·
IP Core design: several memory, arithmetic cores, DSP cores & Telecom
protocols
·
Research work: wrote several papers about technology trends in
business and its effects on design techniques
·
Interests :
·
Intrinsic
motivation for innovation & effects of innovation on the economy
·
Technology
market trends and forecasting
·
CPU,
DSP and arithmetic algorithm design
·
Open
source concept & related business models
Affiliations:
·
Member
of IEEE Computer and Engineering management societies since 1998
·
Leader
member of OpenCores.org & OpenTech project since 2000
·
Co-Founder
& general coordinator of Handasa Arabia organization since 2003
·
Member
of Program Committee of the IEEE IOST3 Workshop, April 2006,
Personal Details:
Date of birth:
Marital
status: Married
Languages
|
Arabic |
English |
German |
Hebrew |
|
Mother language |
Excellent |
Good |
Working knowledge |
Courses & trainings:
Articles and publications:
Please refer to the website for complete list