Partial reconfigurations considerations

Algorithm partitioning is one of the important issues that must be considered while designing an RTR application. In partially reconfigured applications the location of the hardware module ``partition'' is unknown at the design time so this may cause some problems that may reduce the performance of the system. Surrounding circuitry is not known before placing the modules which increases the difficulty of the placing algorithms must be used at run-time [7,10].
Inter-communications and interfacing between hardware modules is more problematic in the partially reconfigured systems than in the totally reconfigured ones. The interfacing between circuits is unknown at the design time and also the sub-circuits need to interact to different sub-circuits dynamically.
Special kind of architectures must be introduced to support the partial reconfiguration technique. For example there must be some predictable circuits timing to ensure that the circuits will behave according to the specifications wherever they are located. Also there must an easy interface to the whole internal resources of the FPGA. Atmel, National and Xilinx have there own versions of partial reconfigurable FPGAs. The XC6200 family from xilinx uses the FastMap^TM interface, which is a dedicated interface to connect the FPGA directly to the host processor without consuming FPGA resources. This interface maps the FPGA resources into the memory address space of the processor, so the configuration of each individual resourced can be read or written by the host processor. Also the CX6200 has a hierarchal routing method that provides predictable routing delays [1,2].