Object Oriented Programming languages are the most suitable languages that can be used for this approach. A hardware module is encapsulated in a single class that inherits the characteristics of its parent (the hardware Object) where most of the common functions are defined like place and route algorithms, load/unload, scheduling and more.
Load and unload problems take the advantage of the built in constructors and destructors in the Object Oriented Programming style. These functions are called when new objects are created or destroyed. They perform the proper initialization and finalization to the object by allocating and deallocating memory. This is exactly what is needed for the hardware objects when they need to be loaded or removed from the FPGA resources.
In general, the application developer must divide his algorithm into hardware objects and software control procedures. TSI Telsys implemented this approach using the Java language for their ACECards where the Java run time environment runs the application on either the ACECard's embedded processor, or the host workstation's processor.[6]
Virtual Computer Corporation ``VCC'' uses the same idea for its RC systems, but instead of using OO language, it uses the C language and header files to encapsulate the hardware objects. The header files are created by a tool that converts the bit-stream file into C like file [5].
The PRISM project uses the GNU C compiler ``gcc'' as the parser and preoptimizer compiler, and the VHDL Designer and X-BLOX for code synthesis. The gcc produces RTL list and VHDL representation of the code while the synthesis tool generates the hardware image that is placed and routed by the hardware vendor tools. After all, the software image that runs on the host processor controls the program and hardware images downloading flow. 2
Several programs have been tested on this system and showed good speed up over the pure software procedures. For more information refer to [15] and [3]
The first approach uses predesigned and preoptimized hardware models that are combined with the software models. Software model interacts with the runtime environment and manages the hardware resources by loading and unloading hardware modules from the FPGA according to the algorithm requirements.
Object Oriented Programming languages are the most suitable languages that can be used for this approach. A hardware module is encapsulated in a single class that inherits the characteristics of its parent (the hardware Object) where most of the common functions are defined like place and route algorithms, load/unload, scheduling and more.
Load and unload problems take the advantage of the built in constructors and destructors in the Object Oriented Programming style. These functions are called when new objects are created or destroyed. They perform the proper initialization and finalization to the object by allocating and deallocating memory. This is exactly what is needed for the hardware objects when they need to be loaded or removed from the FPGA resources.
In general, the application developer must divide his algorithm into hardware objects and software control procedures. TSI Telsys implemented this approach using the Java language for their ACECards where the Java run time environment runs the application on either the ACECard's embedded processor, or the host workstation's processor.[6]
Virtual Computer Corporation ``VCC'' uses the same idea for its RC systems, but instead of using OO language, it uses the C language and header files to encapsulate the hardware objects. The header files are created by a tool that converts the bit-stream file into C like file [5].
The PRISM project took different approach, where the C language is used to describe the whole algorithm and the compiler creates two images, software and hardware images form the pure C code. So it does not depend on predesigned hardware modules because it is the responsibility of the compiler to synthesis the description code and create the hardware image for the critical parts of the code (or as declared by the code writer).
The PRISM project uses the GNU C compiler ``gcc'' as the parser and preoptimizer compiler, and the VHDL Designer and X-BLOX for code synthesis. The gcc produces RTL list and VHDL representation of the code while the synthesis tool generates the hardware image that is placed and routed by the hardware vendor tools. After all, the software image that runs on the host processor controls the program and hardware images downloading flow. 3
Several programs have been tested on this system and showed good speed up over the pure software procedures. For more information refer to [15] and [3]
In contrast, a special HDL dedicated to the reconfigurable systems and CCM can be used to develop reconfigurable computing applications. The JHDL ``Just another HDL'' from BYU uses the Java language to describe the hardware using built in classes for combinational, sequential circuits and wires. It also supports partial reconfiguration through the use of sockets where hardware modules can be plugged or removed.[4]