Future enhancements

Up to now, the designers must check for the appropriateness of the circuits of reconfigurable logic, so most of the design is done by hand. CAD tools must be designed to do automatic partitioning and and maps the hardware modules taking into considerations the surrounding modules and the proper circuit alignment.
Dynamic circuit generation software is one of the important issues that must be discussed [16]. Another important topic is module relocation and hardware removement algorithms in the partial reconfigurable logic.
I think enhanced place and route algorithms should be developed by hardware implementation either by building the algorithms on the hardware or by creating special designs as in the DISC project [17,18].