Scaling Accumulator Multiplier

Introduction

The implementation of this equation in either HW or SW needs intensive computation and consumes much resources. Several solutions has been suggested to implement this operation in HW that has the traditional trade off size vs. speed.

Scaling Accumulator Multiplier

This approach takes the first operand as a parallel load and the other takes it serially. At the input it performs anding operation between the first operand and a bit at a time of the second operand. The result of this operation is iteritivly shifted and accumulated with the old result. The anding operation just passes the first operand to the accomulater-shifter or not according to a bit in the second operand.

1         1011001
0       0000000
1      1011001
1     1011001+
   10010000101

Advantages

• It is half-parallel half-serial algorithm
• It needs less hardware than fully parallel algorithms
• It needs N clock cycles to get the result, where N is the width of the operand
• MSB or LSB can be first entered to the core depending on the shifting operation direction

VHDL implementation

• My implementation
• Luca Gerli suggested a modified code

Differences between the codes

• My design uses a Mux to select between the bits which is controled by a combinational circuit from the counter states.
• In the modified code op2 is registered and shifted each cycle always the MSB is selected. in this case the combinational delay is too small

• My code uses large "AND" operator to and op1 bits with op2 signel bit which may consume large number of Product terms
• The modified code uses adder enable to enable the addition operation when op2 bit is 1.
reduces the combinational delay and the size of the large and operator.

• My code uses if statement that generates a mux
• The modified code uses "OR" operator between msb of res and oldvalue. Internal variable and a concurrentssignement to write the output port "overflow".

• My code has an if count ..else statement that controls most of signal assignments
• The modified code does not has this if..else statment

Resources and references

• Andraka site: Multiplication in FPGAs