Digital RC Speed Control
This is my second version of the digital speed control. The first one was published some years ago at Eric Behr's. Like the previous circuit, it is based only on hardware, no software code being required, and the ICs are cheap and common to find. It can therefore be built by anyone with reasonable experience. No pretension is made on miniaturisation. For me this is fine as I use my speed controller in a model boat, where size and weight are not a problem. This new circuit is simpler, uses one less chip, but should be more reliable. Again the functions of controller and power chopper have been separated. The Chopper circuit can be found from the Contents page. This is how the controller works:
It is assumed that the reader is familiar with the principles of an RC system. In general a transmitter is used to send the information on the position of the joysticks, or switches on a radio carrier wave. The receiver detects the radio signal and decodes out the information into a number of channels. These channel signals are distributed to the servos. The standard RC system uses control signals made up of pulses with a length that can be varied from 1ms to 2ms and repeated after about 20ms.
When the joystick is fully home in one direction, the pulse on the channel is say 1ms long. When you move the stick the pulse gets longer. When the stick is in the middle, the pulse is 1.5ms long. With the stick all the way in the other direction, the pulse is 2ms long. The pulse width changes gradually as you move the stick, getting fatter or thinner in proportion to the stick position. This technique and is called PWM or pulse width modulation. The variations in pulse width are interpreted by the electronics in a normal servo to move the arm through an angle of 90 degrees from one extreme position to the other. This article deals with speed control. As it happens, we shall also be using PWM to control the speed of an electric motor. However the shape of the pulses coming out of the receiver are not suitable to drive directly a motor as the duty cycle varies only by a small amount (a variation from 5% to 10%). To control a motor satisfactorily we need a pulse train whose duty cycle which can be varied from 0% to 100%. This is the job of the speed controller.
The controller is made of three main parts: The up-counter, the latch (or register) and a down-counter. The up-counter which is inside the 74HC590 is used to measure the length of the incoming pulse. By measure I mean that the length of time the pulse is high (logic 1) is converted into a binary number. To do this the counter must be stepped by a suitable clock. A source of clock pulses is therefore needed and this is derived from a crystal oscillator (pin 3 of 4040).
When the incoming pulse returns to zero, then counting is stopped and the binary number in the counter is loaded into the register. This way the number representing the pulse length is saved (or frozen), while the counter can be cleared (zeroed) ready to measure the next pulse. The register is also part of the 590 chip and the value stored in the register is available at pins Q1 to Q8. Both the counter and the register are 8 bits long. The clock rate is such that 2ms are slightly longer then the time needed to count up to H'FF (255). The sequence of events is as follows:
Input goes high - enable counting (pin 12).
While counting enabled, and no carry - count clock pulses (pin 11).
If carry out - stop counting (pin 9 goes low stopping clock pulses from reaching pin 11).
Input goes low - disable counting (pin 12), copy to register (pin 13), clear counter (pin10).
Goto 1 - wait until next input pulse comes along.
The Ripple Carry Out (RCO) is used to stop incrementing the counter when the maximum count is exceeded. This is required as the maximum pulse length actually varies from manufacturer to manufacturer of radio gear and according to joystick trim settings.
On the other end of the range, the counting starts from zero immediately with the start of the pulse. However the actual information starts after the first 1ms has gone by. Since this is right in the middle of the total possible pulse width, then bit 8 is used to indicate when the pulse is greater or less then 1ms. Should the input be less then 1ms, then bit 8 is zero. Above 1ms then bit 8 is 1. Those familiar with binary counting would understand how the lower bits rollover and repeat the pattern after the first 1ms. The actual number of bits used to measure the part of the input from 1ms up to 2ms is thus 7bits. Hence the range is divided into 128 steps. This resolution is far more then is required in practice and much better then many other digital controllers.
OK, so now we have 8 bits that represent in a digital way the width of the input pulse. These are interpreted as:
If bit 8 is zero - output is zero;
If bit 8 is 1 - output is equal to the numeric value of the least 7 bits: from 0000000 to 1111111 (127).
The captured pulse width as a binary number remains frozen in the register until it is updated every 20ms.
The last part of the circuit involves the down-counter 40103. This counter of the 40103 is loaded periodically with the value stored in the register of the 590. Loading is done by means of very narrow pulses on pin 9 (Ape). A clock which is 128 times faster then the loading clock is used to decrement the counter (pin 1). When the count reaches zero the condition is indicated by Zd (zero detect pin 14) going low. This condition is used to stop the countdown by gating the fast clock. The output stays at zero until the counter is then loaded afresh with the next periodic loading pulse. Therefore the time that pin 14 remains high is directly proportional to the value loaded in the counter. Eg if the value was 32, then pin 14 would be high for 32 clock pulses and low for the remaining 96 pulses (25% duty cycle). If the value loaded was 64, then Zd would be high for 64 pulses and low for the other 64 pulses (50%).
The extreme cases would be when the output from the register is all 1s and when bit 8 is zero. In the first instance the down counter will need all of 128 pulses before it reaches zero, by which time it is again loaded and the process repeats (100% duty cycle). On the other extreme we would like that when bit 8 of the register is zero, then Zd remains low. The reset pin of the 4040 (pin 2) cannot be used as this resets the counter to H'FF not 0. The method selected was to use bit 8 to gate the loading pulses. Thus if bit 8 is zero, the counter will not be loaded with a new count value, so when it reaches zero, the output stays there, until bit 8 changes.
The downcounter works at its own rate, independent from the pulses sent by the receiver. It can therefore be clocked and loaded at any rate as long as the relation between the loading pulses and the clocking pulses is maintained (1:128). The clock generator using the 4040 12 stage ripple counter produces a useful range of outputs. The PWM train can therefore be programmed from about 1Khz up to 31Khz. Higher rates are possible by using a different crystal. I personally like the 15KHz rate as this is high enough not to be audible, keeps the motor freewheeling, while low enough to keep switching losses reasonable.
Some comments about the loading circuit. The previous version of the circuit used a 4013 dual flip-flop to form the narrow loading pulses. This worked correctly for loading the 40103 down-counter. The other half of the 4013 was used to control the 590. This part was not correct in that the input was not synchronised with the local clock. This was simply resolved in this new circuit by using the input pulse edges to control the 590. This required just one inverter (4069) gate. The 4013 was subsequently eliminated altogether and the 40103 was loaded by narrow pulses formed by ANDing the clock signal with itself after three gate delays. This is the standard three gate delay configuration with a twist - by controlling it with bit 8 of the 590. The generated pulses are however so narrow that they are very difficult to observe on an oscilloscope. I therefore added the 1nF capacitor to make these a bit wider (still less then 1us).
The final PWM output is obtained from the 40103 pin 14 (Zd). Since I had an extra 4069 gate, I used it to obtain an inverted output. Either of the outputs can be used, depending on what the power chopper needs to see. It is also handy for those who do not have the Servo-Reverse function on their transmitter.
Finally I would like to add that the clock oscillator can use a ceramic resonator instead of a quartz crystal. Resonators are smaller and cheaper then quartz, while the 22pF capacitors might no longer be necessary.
Last updated 22 May 2000
Anthony Psaila