MCS-51 Instruction
ARITHMETIC OPERATIONS
Mnemonic Description

Bytes

Cycles
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDC
SUBB
SUBB
SUBB
SUBB
INC
INC
INC
INC
DEC
DEC
DEC
DEC
INC
MUL
DIV
DA
 A,Rn
A,direct
A, @Ri
A,#data
A,Rn
A,direct
A, @Ri
A,#data
A,Rn
A,direct
A, @Ri
A,#data
A
Rn
direct
@Ri
A
Rn
direct
@Ri
DPTR
AB
AB
A
 Add register to A
Add direct byte to A
Add indirect RAM to A
Add immediate data to A
Add register to A with Carry
Add direct byte to A with Carry
Add indirect RAM to A with Carry
Add immediate data to A with Carry
Subtract register from A with Borrow
Subtract direct byte from A with Borrow
Subtract indirect RAM from A with Borrow
Subtract immediate data from A with Borrow
Incerement A
Increment register
Increment direct byte
Increment indirect RAM
Decrement A
Decrement register
Decrement direct byte
Decrement indirect RAM
Incerement Data Pointer
Multiply A&B (AxB=>BA)
Divide A by B (A/B=>B+A)
Decimal Adjust A

1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
4
4
1


LOGICAL OPERATIONS
Mnemonic Description

Bytes

Cycles
ANL
ANL
ANL
ANL
ANL
ANL
ORL
ORL
ORL
ORL
ORL
ORL
XLR
XLR
XLR
XLR
XLR
XLR
CLR
CPL
RL
RLC
RR
RRC
SWAP
 A,Rn
A,direct
A,@Ri
A,#data
direct,A
direct,#data
A,Rn
A,direct
A,@Ri
A,#data
direct,A
direct,#data
A,Rn
A,direct
A,@Ri
A,#data
direct,A
direct,#data
A
A
A
A
A
A
A
 AND register to A
AND direct byte to A
AND indirect RAM to A
AND immediate data to A
AND A to direct byte
AND immediate data to direct byte
OR register to A
OR direct byte to A
OR indirect RAM to A
OR immediate data to A
OR A to direct byte
OR immediate data to direct byte
Exclusive-OR register to A
Exclusive-OR direct byte to A
Exclusive-OR indirect RAM to A
Exclusive-OR immediate data to A
Exclusive-OR A to direct byte
Exclusive-OR immediate data to direct byte
Clear A
Complement A
Rotate A Left
Rotate A Left trought Carry
Rotate A Right
Rotate A Right trought Carry
Swap nibbles within A

1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1

1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
1
1


DATA TRANSFER
Mnemonic Description

Bytes

Cycles
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVC
MOVC
MOVX
MOVX
MOVX
MOVX
PUSH
POP
XCH
XCH
XCH
XCHD
 A,Rn
A,direct
A,@Ri
A,#data
Rn,A
Rn,direct
Rn,#data
direct, A
direct, Rn
direct, direct
direct, @Ri
direct, #data
@Ri,A
@Ri,direct
@Ri,#data
DPTR,#data16
A,@A+DPTR
A,@A+PC
A,@Ri
A,@DPTR
@Ri,A
@DPTR,A
direct
direct
A,Rn
A,direct
A,@Ri
A,@Ri
 Move register to A
Move direct byte to A
Move indirect RAM to A
Move immediate data to A
Move A to register
Move direct byte to register
Move immediate data to register
Move A to direct byte
Move register to direct byte
Move direct byte to direct byte
Move indirect RAM to direct byte
Move immediate data to direct byte
Move A to indirect RAM
Move direct byte to indirect RAM
Move immediate data to indirect RAM
Load Data Pointer with 16/bit constant
Move Code byte relative to DPTR to A
Move Code byte relative to PC to A
Move External RAM (8-bit addr) to A
Move External RAM (16-bit addr) to A
Move A to External RAM (8-bit addr)
Move A to External RAM (16-bit addr)
Push direct byte onto stack
Pop direct byte from stack
Exchange register with A
Exchange direct with A
Exchange indirect RAM with A
Exchange low/order Digit indirect RAM with A

1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
2
1
1
1
1
1
1
2
2
1
2
1
1

1
1
1
1
1
2
1
1
2
2
2
2
1
2
1
1
2
2
2
2
2
2
2
2
1
1
1
1


BOOLEAN VARIABLE MANIPULATION
Mnemonic Description

Bytes

Cycles
CLR
CLR
SETB
SETB
CPL
CPL
ANL
ANL
ORL
ORL
MOV
MOV
 C
Bit
C
Bit
C
Bit
C,bit
C,/bit
C,bit
C,/bit
C,bit
Bit,C
 Clear Carry flag
Clear direct bit
Set Carry flag
Set direct bit
Complement Carry flag
Complement direct bit
AND direct bit to Carry flag
AND complement of direct bit to Carry flag
OR direct bit to Carry flag
OR complement of direct bit to Carry flag
Move direct bit to Carry flag
Move Carry flag to direct bit

1
2
1
2
1
2
2
2
2
2
2
2

1
1
1
1
1
1
2
2
2
2
1
2


PROGRAM AND MACHINE CONTROL
Mnemonic Description

Bytes

Cycles
ACALL
LCALL
AJMP
LJMP
SJMP
JMP
JZ
JNZ
JC
JNC
JB
JNB
JBC
CJNE
CJNE
CJNE
CJNE
DJNZ
DJNZ
RET
RETI
NOP
 addr11
addr16
addr11
addr16
rel
@A+DPTR
rel
rel
rel
rel
bit,rel
bit,rel
bit,rel
A,direct,rel
A,#data,rel
Rn,#data,rel
@Ri,#data,rel
Rn,rel
direct,rel
 Absolute subroutine call
Long subroutine call
Absolute Jump
Long Jump
Short Jump (relative addr)
Jump indirect relative to DPTR
Jump if A is Zero
Jump if A Not Zero
Jump if Carry flag is set
Jump if No Carry flag
Jump if direct Bit is set
Jump if direct Bit is Not set
Jump if direct Bit is set & Clear bit
Compare direct to A & Jump if Not Equal
Compare immediate to A & Jump if Not Equal
Compare immediate to register & Jump if Not Equal
Compare immediate to indirect & Jump if Not Equal
Decrement register & Jump if Not Zero
Decrement direct byte & Jump if Not Zero
Return from subroutine
Return from interrupt
No operation

2
3
2
3
2
1
2
2
2
2
3
3
3
3
3
3
3
2
3
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1

Notes on data addressing modes

Rn
Direct
@Ri
#data
#data16
bit
 Working register R0-R7
128 internal RAM locations, any I/O port, control or status register
Indirect internal RAM locations addressed by register R0 or R1
8-bit constant included in instruction
8-bit constant included in instruction
128 software flags, any I/O pin,control or status bit

Notes on program addressing modes

rel
addr16
addr11

8-bit offset relative to first byte of following instruction (+127,-128)
Destination address may be anywhere in 64-kByte program address space
Destination address will be wihin same 2-kByte page of program addressSpace as first byte of the following instruction

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