Hardware Interrupt Generation and Acknowledgement - Part 2

The interrupt vector table contains one entry for each device that can raise an interrupt. This table has to be set up by software (the operating system) at system initialization time. Still, the table is used by the hardware, not the software, so the hardware has to know where the table starts. Normally, this is accomplished by putting the table at some location predetermined by the hardware in use.

What does this table contain?

The interrupt vector table entries each contain information that tells the CPU where the interrupt service routine (or ISR) for that device is located. Each device on the system has an ISR that knows how to service that devices interrupts. Thus, one job that has to be done when adding a new kind of device to an operating system is writing the ISR for that device.

In the PDP-11 and family architecture, the way the table points to the ISR is by holding a PC and PS (program counter and process status word) that point to the ISR.

So - the CPU, having received the interrupt vector address does the following (again - this is H/W not S/W):

1. pushes the current PS and PC onto the stack
2. loads the PS and PC from the interrupt vector table into the PS and PC registers. This causes a jump to the ISR pointed to by the PC in the interrupt vector table entry.

At this point in the handling of an interrupt we have switched to software. The ISR which is now being executed is part of the O/S code. The ISR will now do its job (possibly by calling other routines). In our keyboard input example, it would most likely read the character from the device and transfer it into a buffer of some sort. The ISR should also save and restore some amount of state so that the interrupted process is not affected.

When the ISR is done, the saved PS and PC are restored (usually there is a single CPU instruction to do this called something like RTI - for return from interrupt).