Question: What is an interrupt/exception and how do they work?
First - we need some background.
The CPU, memory and I/O devices (peripherals) must all speak to one another to accomplish their respective tasks. This communication is accomplished by having them all connected to a BUS. A BUS allows communication among the connected components.
There are two general kinds of busses, though sometimes the division is not so clear:
The CPU-memory busses connect (of course) the CPU to the memory and tend to be fast. The I/O busses can also be fast, but are used to connect the CPU to the I/O hardware (devices).
Some systems combine the two busses for simplicity and reduced cost. The PDP-11 (one piece of hardware of interest to us in this course) is an example of an architecture doing so.
Contention for access to a bus can be a major system bottleneck especially in a system whose devices support DMA. Think about it.
Here - the CMMU is the "Cache, Memory Management Unit". It supplies the TLB, data and instruction caches, and does virtual to physical address translation - possibly through demand paging. This may not be present at all, or may be incorporated into the CPU.
Busses normally consist of data, address and control lines.
So that all the components don't use the bus at the same time, a "bus protocol" is followed to govern access.
Some peripherals are bus masters which means they can initiate read/write transactions on the BUS. The CPU is always a bus master. Non-bus master components can only respond to read/write requests.
