An exception is exactly the same as an interrupt except that it is generated by the CPU rather than an external device.
Common exceptions include:
Exception vector addresses are defined by the CPU and the O/S designer needs to refer to the hardware manuals to know where to put the exception vectors for each different exception.
Unlike interrupts, exceptions cannot normally be disabled .
Traps are again the same as interrupts except that they are user (process) generated.
In systems that are dual mode, traps can be (and are) used to change the mode from user to priviledged.
Why generate a trap when the mode is changed from user to priviledged?
The reason a trap is generated is that the trap causes the CPU to jump to a known O/S routine (the one at the vector whose address is assigned to the trap). This ensures that when the mode is changed to supervisor mode, the O/S gets control of the CPU. This way a process cannot somehow change modes and still keep control - it is a security feature.
The only way to defeat this would be for a process to install its own routine at the address of the trap service routine, or to install its own trap vector pointing to another trap service routine. But because the trap vector address and the trap service routine are in protected memory, a user-level process cannot do either of these without changing modes. But as soon as it changes modes - control is handed over to the O/S! So either way you are safe.
The trap service routine determines the cause of the trap (normally a result of a system call) and performs the correct operation.
The following figure shows how an interrupt, exception or trap vector address, along with the interrupt vector table is used to find the ISP for that interrupt, trap or exception.
