From: Adam.Bergstrom@um.erisoft.se (Adam Bergstrom) Newsgroups: comp.sys.cbm Subject: VIC-20 extra memory, UPGRADE Date: 27 Oct 1995 06:30:38 GMT Well, I thought about the bus-collision, and found a way of dealing with it (it's actually simpler now). This is the new version, that won't fry the bus when writing to write-protected memory. It has also got 1 less component (a resistor) :) . VIC-20 32k memory expansion (ver. 951026) ========================================= This is one of my contributions to the Commodore 8-bit community. I made this document to show you how to expand the memory of your VIC-20. I designed and built the memory expansion in October 1995. I have built the expansion on a vero-board inside my VIC-20, so the cartridge- port is free. All that is seen outside are three switches (reset, write enable/disable, memoryexpansion on/off). I also plan to make an external memory-cartridge (so I can make some for my friends without opening their precious babies) as soon as I get all the stuff to make PCB:s at work. This new version has removed the trouble with bus-collision. I hope that this document is accurate and that you can get it to work. My hardware DOES work, and has been tested on quite a few programs, both expanded, unexpanded, and cartridgeimages (both 8k and 16k). I will take no responsibility for any damages that may occur when you are trying to use this information. This information is free, and any damages are done by you, not me. Let the old 8-bit computers LIVE ON! Features -------- * 32k RAM in four 8k blocks located in memory at: $2000 (BLK1) $4000 (BLK2) $6000 (BLK3) $A000 (BLK5) This gives you an additional 24k BASIC memory (27,5k total!), and 8k at the cartridge area. * Ability to load and run cartridge-images from disk or tape. * Write enable/disable switch, lets you run copyprotected cartridgeimages. * Switch to enable/disable the whole extra-memory, to let you use an external cartridge, or use the VIC-20 unexpanded. * Reset switch. Parts used ---------- 1 * HY62256, 32kbyte static RAM, 100ns (any 32k SRAM faster than 500ns should be O.K.) 1 * 74LS147, 10-4 line priority encoder 2 * on/off switches 1 * reset switch Some wires and a vero-board to solder all parts on. How to connect it all --------------------- SRAM_X is pin nr X on SRAM. 74_X is pin nr X on 74LS147. VIC_X is pin nr X on VIC expansion port. SWITCHX_Y is switch nr X, pin nr Y. SWITCH1 is write enable/disable. SWITCH2 is expansion enable/disable. SWITCH3 is reset. SRAM_1(A14) - 74_9(A) SRAM_2(A12) - VIC_R(CA12) SRAM_3(A7) - VIC_K(CA7) SRAM_4(A6) - VIC_J(CA6) SRAM_5(A5) - VIC_H(CA5) SRAM_6(A4) - VIC_F(CA4) SRAM_7(A3) - VIC_E(CA3) SRAM_8(A2) - VIC_D(CA2) SRAM_9(A1) - VIC_C(CA1) SRAM_10(A0) - VIC_B(CA0) SRAM_11(D0) - VIC_2(CD0) SRAM_12(D1) - VIC_3(CD1) SRAM_13(D2) - VIC_4(CD2) SRAM_14(GND) - VIC_GND SRAM_15(D3) - VIC_5(CD3) SRAM_16(D4) - VIC_6(CD4) SRAM_17(D5) - VIC_7(CD5) SRAM_18(D6) - VIC_8(CD6) SRAM_19(D7) - VIC_9(CD7) SRAM_20(!CE) - 74_6(C) SRAM_21(A10) - VIC_N(CA10) SRAM_22(!OE) - 74_6(C) SRAM_23(A11) - VIC_P(CA11) SRAM_24(A9) - VIC_M(CA9) SRAM_25(A8) - VIC_L(CA8) SRAM_26(A13) - 74_7(B) SRAM_27(R/W) - VIC_18(CR/W) SRAM_28(VDD) - VIC_21(+5V) 74_1(4) - VIC_10(!BLK1) 74_2(5) - VIC_11(!BLK2) 74_3(6) - VIC_12(!BLK3) 74_4(7) - VIC_13(!BLK5) 74_5(8) - SWITCH1_2 74_6(C) - SRAM_20(!CE) + SRAM_22(!OE) 74_7(B) - SRAM_26(A13) 74_8(GND) - VIC_GND 74_9(A) - SRAM_1(A14) 74_10(9) - SWITCH2_2 74_11(1) - VIC_GND 74_12(2) - VIC_GND 74_13(3) - VIC_GND 74_14(D) - NC 74_15(NC) - NC 74_16(VCC) - VIC_21(+5V) SWITCH1_1 - VIC_18(CR/W) SWITCH1_2 - 74_5(8) SWITCH1_3 - VIC_21(+5V) SWITCH2_1 - VIC_GND SWITCH2_2 - 74_10(9) SWITCH2_3 - VIC_21(+5V) SWITCH3_1 - VIC_GND SWITCH3_2 - VIC_X(RESET) Memory expansion port, seen from the back of the VIC-20 -------------------------------------------------------- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A B C D E F H J K L M N P R S T U V W X Y Z 1 - GND A - GND 2 - CD0 B - CA0 3 - CD1 C - CA1 4 - CD2 D - CA2 5 - CD3 E - CA3 6 - CD4 F - CA4 7 - CD5 H - CA5 8 - CD6 J - CA6 9 - CD7 K - CA7 10 - !BLK1 L - CA8 11 - !BLK2 M - CA9 12 - !BLK3 N - CA10 13 - !BLK5 P - CA11 14 - !RAM1 R - CA12 15 - !RAM2 S - CA13 16 - !RAM3 T - I/O2 17 - VR/W U - I/O3 18 - CR/W V - SO2 19 - !IRQ W - !NMI 20 - NC X - !RESET 21 - +5V Y - NC 22 - GND Z - GND Static memory HY62256 (SRAM), pinconfiguration ----------------------------------------------- +---U---+ A14-|1 28|-VDD A12-|2 27|-R/W A7-|3 26|-A13 A6-|4 25|-A8 A5-|5 24|-A9 A4-|6 23|-A11 A3-|7 22|-!OE A2-|8 21|-A10 A1-|9 20|-!CE A0-|10 19|-D7 D0-|11 18|-D6 D1-|12 17|-D5 D2-|13 16|-D4 GND-|14 15|-D3 +-------+ 74LS147, pinconfiguration ------------------------- +---U---+ 4-|1 16|-VCC 5-|2 15|-NC 6-|3 14|-D 7-|4 13|-3 8-|5 12|-2 C-|6 11|-1 B-|7 10|-9 GND-|8 9|-A +-------+ On/off switch ------------- / / --+-- | | | | ----- | | | 1 2 3 How to contact me ----------------- Snail mail: Adam Bergstrom Storgatan 92,2 903 33 Umea SWEDEN Telephone: +46-90-178490 Internet email: adam.bergstrom@um.erisoft.se +-----------------+-----------------------------------------------+ |Snail-mail work: |E-mail work: adam.bergstrom@um.erisoft.se | | Adam Bergstrom +--------------------------+--------------------+ | Erisoft AB |Memo work: eri.epl.eplabm |Snail-mail home: | | Pendelgatan 2 +--------------------------+ Adam Bergstrom | | Box 4205 |Telephone: | Storgatan 92 | | S-904 06 Umea | Work: +46 (0)90 153136 | S-903 33 Umea | | Sweden | Home: +46 (0)90 178490 | Sweden | +-----------------+--------------------------+--------------------+ | Opinions expressed are my own, not my employer's. | +-----------------------------------------------------------------+