Lab 3 Report

Introduction
This laboratory assignment consist of a Verilog model for an up/down counter, implement it using the XC4010XL chip, assign I/0 pin assignment, generate the bit-pattern configuration file, and use XS40 board to verify the functionality. The up/down counter's inputs include reset, clock signal driven by 12Mhz oscillator, and a 3-bit control signal. The outputs are the 7-segment LED displays. This finite state machine capable of counting up or down sequence depending on the 3-bit control signal. The control signals are tabulated below:

{I2,I1,I0} DIRECTION COMMENT
000 No count Hold counter at 5 (display 5)
001 UP from 1 to 9 Up counter
010 UP form 3 to B every alternate UP counter skipping even numbers
011 UP from 2 to B every alternate UP counter skipping odd numbers
100 Down from F to 3 Down counter
101 Down from 9 to 1 every alternate Down counter skipping even numbers
110 Down from C to 0 every alternate Down counter skipping odd numbers
111 Down counter Plain down counter

Approach
This up/down counter design is a synchronous finite state machine. The 12Mhz oscillator is used to synchronize the transition between states. The counter is model of an explicit Moore finite state machine. The up/down counter is divided into four behavior statements. The first behavior statement generate the timer pulse that driven by the 12Mhz oscillator; the timer is treated as a clock to synchronize the counter to a speed that slow enough so that a specific counting sequence can be displayed its value under the 7-segment LED displays. To reduce the speed of the 12Mhz oscillator to a 1hz oscillator, it requires a modulo 6 million counter to generate one duty cycle of the new clock pulse, which is called timer. The second behavior statement deals with the synchronize the counting sequence using the timer pulse. The third behavior statement describes the next state of the counting sequence depending on the control input signal that stated above. Finally, the fourth behavior statement decodes the counter's output to a 7-segment LED displays.

Procedure
Write the Verilog code according to the specifications stated above (see attachment). The next step is to assign I/O pin assignment using the ".ucf" extension file. The pin assignments are as follow:
NET clock LOC = P13; NET nclr LOC = P44; NET I0 LOC = P45; NET I1 LOC = P46;
NET I2 LOC = P47; NET S0 LOC = P25; NET S1 LOC = P26; NET S2 LOC = P24;
NET S3 LOC = P20; NET S4 LOC = P23; NET S5 LOC = P18; NET S6 LOC = P19;
The following step is synthesize the design for the XC4010XLPC84 device with the speed of 12Mhz. Once synthesis is completed, implement the design with the timing configuration setting mode enable in the option dialog box. The successful implementation will create the bitstream file that contains the configuration for the XC4010XLPC84. The bitstream file has the ".bit" as its extension. Copy this bitstream file into the appropriate Xess directory and begin to download the bit configuration file. The bitstream file can only be download through the MSDOS command. The command is as followed: C:\xstools\bin\xsload file_name.bit.
Once the download is successful, the counting sequence will be displayed accordingly. The desire counting sequence can be displayed by providing the appropriate input control signal using the xsport command. A typical xsport is as followed: C:\xstools\bin\xsport 0011. This is the up counter from 1 to 9 (001). The least significant digit is the reset signal; it is an active-low signal control.

Simulation Results
The functional simulation is run while ignoring the first and fourth behavior statements because it is unnecessary. The only interest of simulation result is to show whether or not the counting sequence functions according to its specifications. The results showed that the counting sequence functions as it is expected (see waveforms).

Analysis
The 7-segment LED displays showed that the transformation of each count is one second interval. In addition, the display is capable of showing all the hexadecimal characters from 0 to F.

Feature Identification
As stated in the XS40 board manual, the XC4000 family FPGA on the XS40 Board stores its configuration in an on-chip RAM which is erased whenever power is interrupted. However, an external serial EEPROM can be placed in the socket U7 to store the FPGA configuration and reload it on power-up. The direction of how to install and configuration the setting of the EEPROM device is given in the following website: http://www.xess.com/FPGA/manual.html.

Conclusion
The XS40 Board's 7-segment displays showed that the counter counts according to its specifications. However, after several failure attempt to develop this counter assignment, an observation suggests that a multiple modules do not work too well. The first attempt of Verilog code consists of multiple modules; each module generates a separate counting sequence and then de-referencing by its hierarchical path to produce the output. Eventhough the simulation showed that the counter functions correctly and the implementation creates the bitstream, but it would not work properly when it is download to the FPGA. However, the second Verilog code consists of a single module and it works just as expected. In essence, it is best to limit to a single module if possible.