module kcontrol (Reset, VDD, GND, StartStop, Sec, Min,
Data, Clk60Hz, Buzzer,
dCareQ, dCareCout, SecLSB, SecMSB,
MinLSB, MinMSB);

input Reset ;
input VDD ;
input GND ;
input StartStop ;
input Sec ;
input Min ;
input [5:0] Data ;
input Clk60Hz ;
output Buzzer ;
output [5:0] dCareQ;
output dCareCout;
output [6:0] SecLSB;
output [6:0] SecMSB;
output [6:0] MinLSB;
output [6:0] MinMSB;


// add your declarations here
wire wBuzzer; //not buzzer signal
wire wStart; //signal to begin count down
wire wLoadMin; //enable minute counter
wire wMinCout; //signal of sec counter carry out
wire wCoutC1; //carry out C1 instantiation
wire [5:0] wQC1; //Q out of C1 instantiation
wire wClkM1; //output of M1 instanstiation
wire wCoutC2; //carry out C2 instanstiation
wire wCoutC3; //carray out C3 instanstiation
wire wClkM2; //output of M2 instanstiation
wire [5:0] wQC4; //Q out of C4 instantiation
wire wClkM3; //output of M3 instantiation
wire wI0; //ky's 1 lost second remedy
wire [5:0] SecOut ; //counter output for display
wire [5:0] MinOut ; //counter output for display

// add your code here
not (wBuzzer,Buzzer);
and (wStart,wBuzzer,StartStop);
or (wLoadMin,Min,Sec);
and (Buzzer,wMinCout,wCoutC2);
assign wI0 = SecOut[5] && SecOut[4] && SecOut[3]&& !SecOut[2] && SecOut[1] && SecOut[0];

//module counter (C, CLR, up_down, load, cnt, datain, cout, Q);
counter C1 (Clk60Hz, Reset, VDD, GND, Sec, Data, wCoutC1, wQC1);
counter C2 (wClkM1, Reset, GND, Sec, wStart, wQC1, wCoutC2, SecOut);
counter C3 (Clk60Hz, Reset, VDD, GND, VDD, Data, wCoutC3, dCareQ);
counter C4 (wClkM2, Reset, VDD, GND, wLoadMin, Data, dCareCout, wQC4);
counter C5 (wClkM3, Reset, GND, wLoadMin, wStart, wQC4, wMinCout, MinOut);

//module mux2x1 (I0, I1, Sel, Out) ;
mux2x1 M1 (wCoutC3, Clk60Hz, Sec, wClkM1) ;
mux2x1 M2 (wCoutC1, Clk60Hz, Min, wClkM2) ;
mux2x1 M3 (wI0, wClkM2, wLoadMin, wClkM3) ;

//module decode1 (In,Out) ;
decode1 D1 (SecOut,SecMSB) ;
decode1 D3 (MinOut,MinMSB) ;

//module decode2 (In2,Out2) ;
decode2 D2 (SecOut,SecLSB) ;
decode2 D4 (MinOut,MinLSB) ;

endmodule

//This is a up/down counter with parallel load. It will count
//from 0-59 or 59-0 depends on the selection. Cout is asserted
//when counter counts down to 0.
//Control priority: CLR is highest, load, and then cnt last.
module counter (C, CLR, up_down, load, cnt, datain, cout, Q);
//inputs signals
input C, CLR, up_down, load, cnt;
input [5:0] datain;
//output signals
output [5:0] Q;
output cout;
//register declarations
reg [5:0] Q;

//behavior statememt
always @(posedge C or posedge CLR)
begin
if (CLR)
Q = 6'b000000;
else
begin
if (load)
Q = datain;
else
if (up_down && cnt)
begin
Q = Q + 1'b1;
if (Q == 6'b111100) //if count up to 59, reset
Q = 6'b000000;
end
else if (!up_down && cnt)
begin
if (Q == 6'b000000) //if count down to 0, decrement from 59
Q = 6'b111100;
Q = Q - 1'b1;
end
end //outer most else statement
end

assign cout = !Q[5] && !Q[4] && !Q[3] && !Q[2] && !Q[1] && !Q[0];

endmodule

module decode1 (In,Out) ;

input [5:0] In;
output [6:0] Out ;

// add your declarations here
reg [6:0] Out;
// add your code here

always @ (In)
begin
case (In)
0,1,2,3,4,5,6,7,8,9 : Out = 7'b0111111;
10,11,12,13,14,15,16,17,18,19 : Out = 7'b0000110;
20,21,22,23,24,25,26,27,28,29 : Out = 7'b1011011;
30,31,32,33,34,35,36,37,38,39 : Out = 7'b1001111;
40,41,42,43,44,45,46,47,48,49 : Out = 7'b1100110;
50,51,52,53,54,55,56,57,58,59 : Out = 7'b1101101;
60,61,62,63 : Out = 7'b0111111;
default : Out = 7'b0111111;
endcase
end
endmodule

module decode2 (In2,Out2) ;

input [5:0] In2;
output [6:0] Out2 ;

// add your declarations here
reg [6:0] Out2;
// add your code here

always @ (In2)
begin
case (In2)

0: Out2 = 7'b0111111;
10,20,30,40,50 : Out2 = 7'b0111111; //display 0
1,11,21,31,41,51 : Out2 = 7'b0000110; //display 1
2,12,22,32,42,52 : Out2 = 7'b1011011; //display 2
3,13,23,33,43,53 : Out2 = 7'b1001111; //display 3
4,14,24,34,44,54 : Out2 = 7'b1100110; //display 4
5,15,25,35,45,55 : Out2 = 7'b1101101; //display 5
6,16,26,36,46,56 : Out2 = 7'b1111101; //display 6
7,17,27,37,47,57 : Out2 = 7'b0000111; //display 7
8,18,28,38,48,58 : Out2 = 7'b1111111; //display 8
9,19,29,39,49,59 : Out2 = 7'b1100111; //display 9
60,61,62,63 : Out2 = 7'b0111111; //display 0

default : Out2 = 7'b0111111;
endcase
end
endmodule

module mux2x1 (I0, I1, Sel, Out) ;

input I0 ;
input I1 ;
input Sel ;
output Out ;

// add your declarations here
reg Out;
// add your code here
always @ (Sel or I0 or I1)
begin
case (Sel)
0 : Out = I0;
1 : Out = I1;
default : Out = I0;
endcase
end

endmodule