Publications of Chittaranjan Mandal

Journal Publications

  1. A Fast Exploration Procedure for Analog High-Level Specification Translation, IEEE Transactions on CAD, pp 000-000, vol. 00, No. 0, 2008; Soumya Pandit, S K Bhattacharya, C Mandal, Amit Patra. (Abstract)
  2. An Equivalence Checking Method for Scheduling Verification in High-level Synthesis, IEEE Transactions on CAD, pp 556-569, vol. 27, No. 3, 2008; C Karfa, D Sarkar, C Mandal, Pramod Kumar. (Abstract)
  3. A System for Automatic Evaluation of `C' Programs - features and interfaces, International Journal of Web-Based Learning and Teaching Technologies (IJWLTT), pp 24-39, vol. 2, No. 4, 2007; Amit Mandal, C Mandal, Chris Reade. (Abstract)
  4. Web-based Course management and Web Services, Electronic Journal of e-Learning, pp 135-144, vol. 2, No. 1, 2004; C Mandal, Vijaya Luxmi Sinha, Chris Reade. (Abstract / PDF paper)
    1. Listed in Educause CONNECT -- transforming education through information technologies, link
  5. Genetic Algorithms for High-Level Synthesis in VLSI Design, Materials and Manufacturing Processes, pp 355-383, vol. 18, No. 3, 2003; C. Mandal, P. P. Chakrabarti. (Text abstract / PDF paper).
  6. GABIND: A Genetic Algorithm Approach to Allocation and Binding for the High-Level Synthesis of Data Paths, IEEE Transactions on VLSI, pp 747-750, vol. 8, No. 6, December 2000; C. Mandal, P. P. Chakrabarti, S. Ghose. (Text abstract / PDF paper).
    1. Xuejun Tan , Bir Bhanu, Fingerprint matching by genetic algorithms, Pattern Recognition, v.39 n.3, p.465-477, March, 2006
    2. An Evolutionary Algorithm for the Allocation Problem in High-Level Synthesis Harmanani H, Saliba Rony, Journal of Circuits, Systems, and Computers, World Scientific Publishing, vol 14, no 2, pp 347-366, April 2005
    3. Scheduling and allocation using closeness tables, Burns, F. Shang, D. Koelmans, A. Yakovlev, A., Proceedings of the IEE, Computers and Digital Techniques, pp 332-340, vol 151, issue 5, Sept 2004, link
  7. A Design Space Exploration Scheme for Data Path Synthesis, IEEE Transactions on VLSI, pp 331-338, vol. 7, No. 3, 1999; C. A. Mandal, P. P. Chakrabarti, S. Ghose. (Text abstract / PDF paper).
    1. Design Exploration With Imprecise Latency and Register Constraints, Chantana Chantrapornchai, Wanlop Surakampontorn, Edwin Hsing-Mean Sha, pp 2650-2662, IEEE TCAD (ICS), vol. 25, no. 12, December 2006
    2. A design framework to efficiently explore energy-delay tradeoffs, William Fornaciari, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria, pp 260--265, 9th. International Symposium on Hardware/Software Co-Design, 2001, Copenhagen, Denmark
    3. Dealing with Imprecise Timing Information in. Architectural Synthesis. Chantana Chantrapornchai, Surakumpolthorn Wanlop, SHA Edwin, X. Hu, Research report: Technical Report TR-98-5, University of Notre Dame, 1998
    4. Design Exploration Framework under Impreciseness based on Inclusion Scheduling, with W. Surakumpolthorn, E. H-M. Sha, Lecture Notes in Computer Science: Advances in Computing Science -- ASIAN'04, Chiang Mai, Thailand, 2004, pages 78-93.
    5. Presentation by Senthil Kumar Rangaswamy in the course CPE 490/590, University of Alabama in Huntsville,
  8. A Probabilistic Estimator for the Vertex Deletion Problem, Computers and Mathematics with Applications, pp 1-4, vol 35, No. 6, 1998; C. A. Mandal, P. P. Chakrabarti, S. Ghose. (Text abstract / postscript paper).
  9. Complexity of Fragmentable Object Bin Packing and an Application, Computers and Mathematics with Applications, pp. 91-97, vol. 35, No.11, 1998; C. A. Mandal, P. P. Chakrabarti, S. Ghose. (Text abstract / PDF paper).
    1. Approximation schemes for packing with item fragmentation, Shachnai, H., Tamir, T., Yehezkely, O., Theory of Computing Systems 43 (1), pp. 81-98, 2008 Fast asymptotic FPTAS for packing fragmentable items with costs, Shachnai, H., Yehezkely, O., Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 4639 LNCS, pp. 482-493, 2007 Elastic reservations for efficient bandwidth utilization in LambdaGrids, Naiksatam, S., Figueira, S., Future Generation Computer Systems 23 (1), pp. 1-22, 2007 Approximation schemes for packing with item fragmentation, Shachnai, H., Tamir, T., Yehezkely, O., Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 3879 LNCS, pp. 334-347, 2006 Edward G. Coffman, Jr., János Csirik, David S. Johnson, Gerhard J. Woeginger; An Introduction to Bin packing; May, 2004 Nir Naaman, Raphael Rom; Packet Scheduling with Fragmentation; IEEE Infocom; 2002 Nir Menakerman, Raphael Rom: Analysis of Transmissions Scheduling with Packet Fragmentation; Discrete Mathematics & Theoretical Computer Science 4(2): 139-156 (2001) Nir Menakerman and Raphael Rom; Bin Packing with Item Fragmentation; Lecture Notes in Computer Science; Algorithms and Data Structures : 7th International Workshop, WADS 2001, Providence, RI, USA, August, 8-10, 2001, Proceedings;vol 2125, pp 313-324; 2001; F. Dehne, J.-R. Sack, R. Tamassia (Eds.); ISSN: 0302-9743
  10. Some New Results in the Complexity of Allocation and Binding in Data Path Synthesis, Computers and Mathematics with Applications, pp 93-105, vol 35, No. 10, 1998; C. A. Mandal, P. P. Chakrabarti, S. Ghose. (Text abstract / postscript paper).
    1. Platform-based resource binding using a distributed register-file microarchitecture, Jason Cong and Yiping Fan and Wei Jiang, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, pp 709--715, 2006, San Jose, California
    2. A proposal of a greedy-GA combined algorithm for data transfer binding problems, Yasuhito Shikata, Nobuo Funabiki, Junji Kitamichi, Electronics and Communications in Japan (Part III: Fundamental Electronic Science), pp 13-22, vol 84, no 5, 2001
  11. Complexity of Scheduling in High Level Synthesis, VLSI DESIGN, pp 337-346, vol. 7, No. 4, 1998; C. A. Mandal, P. P. Chakrabarti, S. Ghose. (Text abstract / postscript paper)
    1. An Efficient List-Based Scheduling Algorithm for High-Level-Synthesis, Sllame Azeddien M., Drábek Vladimír, EUROMICRO Symposium on Digital System Design: Architecture, Methods and Tools, Dortmund, Germany, 2002, link
  12. Register-Interconnect Optimization in Data Path Synthesis, Microprocessing and Microprogramming, pp. 279-288, vol. 33, 1991; C. A. Mandal, P. P. Chakrabarti, S. Ghose.
  13. Allocation of registers to multiport memories based on register-interconnect optimization, Modelling and Simulation, pp. 57-64, vol. 25, no. 4, 1991; C. A. Mandal, P. P. Chakrabarti, S. Ghose.

Conference/Seminar Proceedings

  1. Verification of Data-path and Controller Generation Phase of High-level Synthesis Proceedings of 15th International IEEE Conference on Advanced Computing & Communication (ADCOM 2007) IIT Guwahati, India, pp 315-320, December 18-21, 2007, Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal (Text abstract / PDF paper / award)
  2. Automatic Detection of Human Fall in Video Proceedings of Second International Conference on Pattern Recognition and Machine Intelligence (PReMI'07), Calcutta, India, pp 616--623, December 18-22, 2007, Vinay Vishwakarma, Chittaranjan Mandal, Shamik Sural (Text abstract)
  3. Hand-in-hand verification of high-level synthesis, Proceedings of IEEE 17th great lakes symposium on Great lakes symposium on VLSI (GLSVLSI'07) Stresa-Lago Maggiore, Italy, pp 429--434, March 11-13, 2007, Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal, Chris Reade (Text abstract / PDF paper)
  4. Register Sharing Verification During Data-path Synthesis, Proceedings of IEEE International Conference on Computing, Theory and Applications (ICCTA'07), Calcutta, India, pp 135-140, March 5-7, 2007, C Karfa, C Mandal, D Sarkar, Chris Reade. (Text abstract / PDF paper)
  5. Coordinator Rotation via Domatic Partition in Self-Organizing Sensor Networks Proceedings of the International Symposium of Wireless Pervasive Computing 2007, San Juan, Puerto Rico, 6 pages, February 5-7, 2007, Rajiv Misra, Chittaranjan Mandal, Ratan Guha
  6. A Scheme for Recipient Specific Yet Anonymous and Tranferable Electronic Cash Proc. of WEBIST 2007 Barcelona, Spain, Setúbal, pp 204-209, March 3-6, 2007, Chittaranjan Mandal, Chris Reade, (Text abstract / PDF paper)
  7. ClusterHead Rotation via Domatic Partition in Self-Organizing Sensor Networks 2nd International Conference on Communication Systems Software and Middleware (COMSWARE 2007), Bangalore, 7 pages, 7-12 January, 2007, Rajiv Misra, Chittaranjan Mandal (Text abstract / slides / award - pdf, jpg)
  8. A Formal Approach for High Level Synthesis of Linear Analog Systems, Proceedings of ACM/IEEE GLSVLSI 2006, Philadelphia, USA, pp 345-348, April 30 -- May 2, 2006, Soumya Pandit, Chittaranjan Mandal, Amit Patra (Text abstract / PDF paper)
  9. Asynchronous Design Methodology for an Efficient Implementation of Low Power ALU Proceedings of IEEE APCCAS2006, Singapore, pp 590-593, 4-7 Dec, 2006, Manikandan P, Liu B D, Chiou L Y, Sundar G, Mandal C R (Text abstract / PDF paper / award)
  10. A Hybrid Search Procedure for System-Level Analog Design Space Exploration used in High Level Synthesis of Analog Systems. (CIS-23) Proceedings of IEEE CODEC-06, Hyatt Regency, Saltlake, 18-20 Dec, 2006, Soumya Pandit, C R Mandal, Amit Patra
  11. A Formal Verification Method of Scheduling in High-level Synthesis, Proceedings of ACM/IEEE 7th International Symposium on Quality Electronic Design (ISQED 2006), San Jose, USA, pp 71-78, March 27-29, 2006, Chandan Karfa, Chittaranjan Mandal, Dipankar Sarkar, Satyam R Pentakota, Chris Reade, ISBN: 0-7695-2523-7. (Text abstract / PDF paper/ slides)
    1. Thanyapat Sakunkonchak, Takeshi Matsumoto, Hiroshi Saito, Satoshi Komatsu, Masahiro Fujita, Equivalence checking in C-based system-level design by sequentializing concurrent behaviors, Proceedings of the third conference on IASTED International Conference: Advances in Computer Science and Technology, p.36-42, April 02-04, 2007, Phuket, Thailand, link
    2. Tsung-Hsi Chiang, Lan-Rong Dung, Verification method of dataflow algorithms in high-level synthesis, Journal of Systems and Software, v.80 n.8, p.1256-1270, August, 2007, link
  12. Ant-aggregation: Ant Colony Algorithm for optimal data aggregation in Wireless Sensor Networks, Proceedings of the Third IEEE and IFIP International Conference on Wireless and Optical Communications Networks (WOCN 2006), Le Meridien, Bangalore, India, Apr 11-13, 2006, Rajiv Misra, Chittaranjan Mandal (Text abstract / PDF paper)
  13. Animating Algorithms over the Web Proc. of WEBIST 2006 , Setúbal, Portugal, pp 403-407, Apr 11-13, 2006, Chittaranjan Mandal, Chris Reade, ISBN 978-9728865-47-4. (Text abstract / PDF paper)
  14. A System for Automatic Evaluation of Programs for Correctness and Performance Proc. of WEBIST 2006, Setúbal, Portugal, pp 196-203, Apr 11-13, 2006, Amit Kumar Mandal, Chittaranjan Mandal, Chris Reade, ISBN 978-9728865-47-4. (Text abstract / PDF paper)
  15. Verification of Scheduling in High-level Synthesis, Proceedings of IEEE Computer Society Annual Symposium on VLSI, Karlsruhe, Germany, pp 141-146, Mar 2-3, 2006, Chandan Karfa, S R Pentakota, Chittaranjan Mandal, Dipankar Sarkar, Chris Reade. (Text abstract / PDF paper)
  16. A Technique for Algorithm Animation Over the Web, Proc. of International Conference on Emerging Applications of IT, Elsevier, Science City, Calcutta, pp 163-166, Feb 10-11, 2006, Chittaranjan Mandal, Chris Reade. (Text abstract / PDF paper)
  17. High-level Synthesis of Linear Analog Systems, Proc. of International Conference on Emerging Applications of IT, Elsevier, Science City, Calcutta, pp 389-392, Feb 10-11, 2006, Soumya Pandit, Chittaranjan Mandal, Amit Patra. (Text abstract / PDF paper / slides)
  18. An Efficient Algorithm for scheduling verification, Proc. of International Conference on Emerging Applications of IT, Elsevier, Science City, Calcutta, pp 397-400, Feb 10-11, 2006, Chandan Karfa, S R Pentakota, Chittaranjan Mandal, Dipankar Sarkar, Chris Reade. (Text abstract / PDF paper)
  19. Design and Implementation of an Automatic Program Evaluation System, Proc. of International Conference on Emerging Applications of IT, Elsevier, Science City, Calcutta, pp 325-328, Feb 10-11, 2006, Amit Mandal, Chittaranjan Mandal, Chris Reade. (Text abstract / PDF paper)
  20. High Level Synthesis of Higher Order Continuous Time State Variable Filter with Minimum Sensitivity and Hardware Count, Proceedings of DATE 06, ICM, Munich, Germany, pp 1203-1204, Mar 6-10, 2006, Soumya Pandit, Chittaranjan Mandal, Amit Patra. (Text abstract / PDF paper)
  21. Optimal Clustering in Sensor Networks Using Game-theoretic Particle Swarm Optimization, Proc. of the 4th Asian International Mobile Computing Conference (AMOC 2006), Hyatt Regency, Calcutta, India, pp 114-118, Jan 4-7, 2006, Rajiv Misra, Chittaranjan Mandal, ISBN: 0-07-060834-2. (Text abstract / PDF paper)
  22. An Improved Energy Efficient Distributed Clustering Algorithm for Large Wireless Sensor Networks, Proc. of the 4th Asian International Mobile Computing Conference (AMOC 2006), Hyatt Regency, Calcutta, India, pp 95-104, Jan 4-7, 2006, Rajiv Misra, Chittaranjan Mandal, ISBN: 0-07-060834-2. (Text abstract / PDF paper)
  23. Self-Healing for Self-Organizing Cluster Sensor Networks, Proc. of IEEE 2006 Annual India Conference (INDICON 2006), India Habitat Centre, New Delhi, India, Sept 15-17, 2006, Rajiv Misra, Chittaranjan Mandal
  24. SAST: An Interconnection Aware High-Level Synthesis Tool, Proc. of the 9th VLSI Design & Test Symposium (VDAT), Bangalore, India, pp 285-293, August 11-13, 2005, C R Mandal, D Sarkar, C Karfa, J S Reddy, S Biswas. (Text abstract / PDF paper / Slides)
  25. Performance comparison of AODV/DSR on-demand routing protocols for ad hoc networks in constrained situation, Proceedings of IEEE International Conference on Personal Wireless Communications, 2005 (ICPWC 2005), New Delhi, India, pp 86-89, January 23-25, 2005, Misra, R., Mandal, C.R. (Text abstract / PDF paper)
  26. A Web-based Automatic Evaluation System, Proc. of the 3rd European Conference on eLearning, Paris, France, pp 189-196, 25-26 November 2004, C Mandal, V L Sinha, C M P Reade. (Text abstract / Extended abstract / PDF paper / presentation slides)
  27. A New Approach to Timing Analysis using Event Propagation and Temporal Logic, Proceedings of DATE '04, Paris, France, pp 1198 - 1203, 2004, Arijit Mondal, Partha P Chakrabarti, C Mandal. (Text abstract / PDF paper)
  28. A Web-Based Course Management Tool, Proc. of the 2nd European Conference on e-Learning, Nov 6-7, Glasgow, UK, pp 293-302, 2003, C. Mandal, V. L. Sinha, C. M. P. Reade. (Text abstract / PDF paper)
  29. Timing Analysis of Tree-like RLC Circuits, Proceedings of IEEE International Symposium on Circuits and Systems, Scottsdale, Arizona, USA, pp. 838-841, 2002, Rajendran, B., Kheterpal, V., Das, A., Majumder, J., Mandal, C., Chakrabarti, P.P. (Text abstract / PDF paper)
  30. A Genetic Algorithm for the Synthesis of Structured Data Paths, Proceedings of IEEE VLSI Design 2000, Calcutta, INDIA, pp. 206-211, 2000; C. Mandal, R. M. Zimmer. (Text abstract / PDF paper)
  31. Integrated Scheduling and Allocation for Synthesis of Structured Data Paths, Proceedings of IEEE VLSI Design & Test Workshops, August 6-7, 1998, The Habitat World, Lodi Road, New Delhi, India, on-line proceedings; C. Mandal, R. Zimmer. (Text abstract)
  32. High-Level Synthesis of Structured Data Paths, Proc. of IFIP TC10 WG 10.5 International Conference on Computer Hardware Description Languages and Their Applications, 20-25 April 1997, Toledo, Spain; pp. 92-94; C. A. Mandal, R. M. Zimmer. (Extended version available) (Text abstract / postscript paper)
  33. Design Space Exploration for Data Path Synthesis, Proceedings of IEEE VLSI Design '97, Hydrabad, INDIA, pp. 166-173, 1997; C. A. Mandal, P. P. Chakrabarti, S. Ghose. (Text abstract / PDF paper)
    1. Efficient Scheduling for Design Exploration with Imprecise Latency and Register Constraints, Chantrapornchai Chantana, Surakumpolthorn Wanlop, SHA Edwin pp 259-270, Embedded and ubiquitous computing, 2004, link
  34. Allocation and Binding for Data Path Synthesis Using a Genetic Approach, Proceedings of the Ninth International Conference on VLSI Design, Bangalore, INDIA, 3-6 January, pp. 122-125, 1996; C. A. Mandal, P. P. Chakrabarti, S. Ghose. (Text abstract / PDF paper)
    1. An Indexed Bibliography of Genetic Algorithms in Electronics and VLSI Design and Testing, A. Jarmo, 1994, link
  35. Port Assignment for Dual and Triple Port Memories Using a Genetic Approach, Proceedings of IFIP Asia/Pacific Conference on Hardware Description Languages, Bangalore, INDIA, pp. 60-64, 1996; C. A. Mandal, P. P. Chakrabarti, S. Ghose. (Text abstract / postscript paper)
  36. Use of Multi-Port Memories in Programmable Structures for Architectural Synthesis, Proceedings of the Eighth Annual IEEE International Conference on Innovative Systems in Silicon, Austin, 9-11 October, pp. 341-351, 1996; C. A. Mandal, R. M. Zimmer. (PDF paper)
  37. Allocation of Registers to Multi-port Memories Based on Register--Interconnect Optimization, Proceedings of ICAUTO -International Conference- 1995, Indore, pp. 611-614, 1995; C. A. Mandal, P. P. Chakrabarti, S. Ghose.
  38. A Framework for High Level Synthesis, International Workshop on Artificial Intelligence, I.I.M., Calcutta, March, 1994; C. A. Mandal, P. P. Chakrabarti, S. Ghose.
  39. Complexity of Scheduling 2-Operation Chains and Some Other Related Scheduling Problems, Proceedings of the Fourth National Seminar on Theoretical Computer Science, IIT Kanpur, INDIA, pp. 171-180, 1994; C. A. Mandal, P. P. Chakrabarti, S. Ghose.
  40. Interconnect Optimization Techniques in Data Path Synthesis, Proceedings of IEEE VLSI Design '92, Bangalore, pp. 85-90, 1991; C. A. Mandal, P. P. Chakrabarti, S. Ghose. (PDF paper)
  41. ABS: An Automated Behavioural Synthesis System, Proceedings of VLSI Design '90, Bangalore, pp. 18-23, 1991; C. A. Mandal, P. Pal Chaudhuri.

Book Chapter

Mandal, A., Mandal, C., Reade, C. (2007), A System for Automatic Evaluation of Programs for Correctness and Performance, in J. Filipe, J. Cordeiro, and V. Pedrosa (Eds.), Web Information Systems and Technologies I, pp. 367-380, Lecture Notes in Business Information Processing (LNBIP), Springer-Verlag, Berlin-Heidelberg.

PhD Thesis

Complexity Analysis and Algorithms for Data Path Synthesis.
Abstract of thesis.

Selected Student Theses

1