The make utility automatically determines which pieces of a large
program need to be recompiled, and issues commands to recompile them.
This manual describes GNU make, which was implemented by Richard
Stallman and Roland McGrath. Development since Version 3.76 has been
handled by Paul D. Smith.
GNU make conforms to section 6.2 of IEEE Standard
1003.2-1992 (POSIX.2).
Our examples show C programs, since they are most common, but you can use
make with any programming language whose compiler can be run with a
shell command. Indeed, make is not limited to programs. You can
use it to describe any task where some files must be updated automatically
from others whenever the others change.
To prepare to use make, you must write a file called
the makefile that describes the relationships among files
in your program and provides commands for updating each file.
In a program, typically, the executable file is updated from object
files, which are in turn made by compiling source files.
Once a suitable makefile exists, each time you change some source files,
this simple shell command:
make
suffices to perform all necessary recompilations. The make program
uses the makefile data base and the last-modification times of the files to
decide which of the files need to be updated. For each of those files, it
issues the commands recorded in the data base.
You can provide command line arguments to make to control which
files should be recompiled, or how. See section How to Run make.
If you are new to make, or are looking for a general
introduction, read the first few sections of each chapter, skipping the
later sections. In each chapter, the first few sections contain
introductory or general information and the later sections contain
specialized or technical information.
The exception is section An Introduction to Makefiles,
all of which is introductory.
If you are familiar with other make programs, see section Features of GNU make, which lists the enhancements GNU
make has, and section Incompatibilities and Missing Features, which explains the few things GNU make lacks that
others have.
If you have problems with GNU make or think you've found a bug,
please report it to the developers; we cannot promise to do anything but
we might well want to fix it.
Before reporting a bug, make sure you've actually found a real bug.
Carefully reread the documentation and see if it really says you can do
what you're trying to do. If it's not clear whether you should be able
to do something or not, report that too; it's a bug in the
documentation!
Before reporting a bug or trying to fix it yourself, try to isolate it
to the smallest possible makefile that reproduces the problem. Then
send us the makefile and the exact results make gave you. Also
say what you expected to occur; this will help us decide whether the
problem was really in the documentation.
Once you've got a precise problem, please send electronic mail to:
bug-make@gnu.org
Please include the version number of make you are using. You can
get this information with the command `make --version'.
Be sure also to include the type of machine and operating system you are
using. If possible, include the contents of the file `config.h'
that is generated by the configuration process.
You need a file called a makefile to tell make what to do.
Most often, the makefile tells make how to compile and link a
program.
In this chapter, we will discuss a simple makefile that describes how to
compile and link a text editor which consists of eight C source files
and three header files. The makefile can also tell make how to
run miscellaneous commands when explicitly asked (for example, to remove
certain files as a clean-up operation). To see a more complex example
of a makefile, see section Complex Makefile Example.
When make recompiles the editor, each changed C source file
must be recompiled. If a header file has changed, each C source file
that includes the header file must be recompiled to be safe. Each
compilation produces an object file corresponding to the source file.
Finally, if any source file has been recompiled, all the object files,
whether newly made or saved from previous compilations, must be linked
together to produce the new executable editor.
A simple makefile consists of "rules" with the following shape:
target ... : prerequisites ...
command
...
...
A target is usually the name of a file that is generated by a
program; examples of targets are executable or object files. A target
can also be the name of an action to carry out, such as `clean'
(see section Phony Targets).
A prerequisite is a file that is used as input to create the
target. A target often depends on several files.
A command is an action that make carries out.
A rule may have more than one command, each on its own line.
Please note: you need to put a tab character at the beginning of
every command line! This is an obscurity that catches the unwary.
Usually a command is in a rule with prerequisites and serves to create a
target file if any of the prerequisites change. However, the rule that
specifies commands for the target need not have prerequisites. For
example, the rule containing the delete command associated with the
target `clean' does not have prerequisites.
A rule, then, explains how and when to remake certain files
which are the targets of the particular rule. make carries out
the commands on the prerequisites to create or update the target. A
rule can also explain how and when to carry out an action.
See section Writing Rules.
A makefile may contain other text besides rules, but a simple makefile
need only contain rules. Rules may look somewhat more complicated
than shown in this template, but all fit the pattern more or less.
Here is a straightforward makefile that describes the way an
executable file called edit depends on eight object files
which, in turn, depend on eight C source and three header files.
In this example, all the C files include `defs.h', but only those
defining editing commands include `command.h', and only low
level files that change the editor buffer include `buffer.h'.
We split each long line into two lines using backslash-newline; this is
like using one long line, but is easier to read.
To use this makefile to create the executable file called `edit',
type:
make
To use this makefile to delete the executable file and all the object
files from the directory, type:
make clean
In the example makefile, the targets include the executable file
`edit', and the object files `main.o' and `kbd.o'. The
prerequisites are files such as `main.c' and `defs.h'.
In fact, each `.o' file is both a target and a prerequisite.
Commands include `cc -c main.c' and `cc -c kbd.c'.
When a target is a file, it needs to be recompiled or relinked if any
of its prerequisites change. In addition, any prerequisites that are
themselves automatically generated should be updated first. In this
example, `edit' depends on each of the eight object files; the
object file `main.o' depends on the source file `main.c' and
on the header file `defs.h'.
A shell command follows each line that contains a target and
prerequisites. These shell commands say how to update the target file.
A tab character must come at the beginning of every command line to
distinguish commands lines from other lines in the makefile. (Bear in
mind that make does not know anything about how the commands
work. It is up to you to supply commands that will update the target
file properly. All make does is execute the commands in the rule
you have specified when the target file needs to be updated.)
The target `clean' is not a file, but merely the name of an
action. Since you
normally
do not want to carry out the actions in this rule, `clean' is not a prerequisite of any other rule.
Consequently, make never does anything with it unless you tell
it specifically. Note that this rule not only is not a prerequisite, it
also does not have any prerequisites, so the only purpose of the rule
is to run the specified commands. Targets that do not refer to files
but are just actions are called phony targets. See section Phony Targets, for information about this kind of target. See section Errors in Commands, to see how to cause make to ignore errors
from rm or any other command.
By default, make starts with the first target (not targets whose
names start with `.'). This is called the default goal.
(Goals are the targets that make strives ultimately to
update. See section Arguments to Specify the Goals.)
In the simple example of the previous section, the default goal is to
update the executable program `edit'; therefore, we put that rule
first.
Thus, when you give the command:
make
make reads the makefile in the current directory and begins by
processing the first rule. In the example, this rule is for relinking
`edit'; but before make can fully process this rule, it
must process the rules for the files that `edit' depends on,
which in this case are the object files. Each of these files is
processed according to its own rule. These rules say to update each
`.o' file by compiling its source file. The recompilation must
be done if the source file, or any of the header files named as
prerequisites, is more recent than the object file, or if the object
file does not exist.
The other rules are processed because their targets appear as
prerequisites of the goal. If some other rule is not depended on by the
goal (or anything it depends on, etc.), that rule is not processed,
unless you tell make to do so (with a command such as
make clean).
Before recompiling an object file, make considers updating its
prerequisites, the source file and header files. This makefile does not
specify anything to be done for them--the `.c' and `.h' files
are not the targets of any rules--so make does nothing for these
files. But make would update automatically generated C programs,
such as those made by Bison or Yacc, by their own rules at this time.
After recompiling whichever object files need it, make decides
whether to relink `edit'. This must be done if the file
`edit' does not exist, or if any of the object files are newer than
it. If an object file was just recompiled, it is now newer than
`edit', so `edit' is relinked.
Thus, if we change the file `insert.c' and run make,
make will compile that file to update `insert.o', and then
link `edit'. If we change the file `command.h' and run
make, make will recompile the object files `kbd.o',
`command.o' and `files.o' and then link the file `edit'.
Such duplication is error-prone; if a new object file is added to the
system, we might add it to one list and forget the other. We can eliminate
the risk and simplify the makefile by using a variable. Variables
allow a text string to be defined once and substituted in multiple places
later (see section How to Use Variables).
It is standard practice for every makefile to have a variable named
objects, OBJECTS, objs, OBJS, obj,
or OBJ which is a list of all object file names. We would
define such a variable objects with a line like this in the
makefile:
Then, each place we want to put a list of the object file names, we can
substitute the variable's value by writing `$(objects)'
(see section How to Use Variables).
Here is how the complete simple makefile looks when you use a variable
for the object files:
objects = main.o kbd.o command.o display.o \
insert.o search.o files.o utils.o
edit : $(objects)
cc -o edit $(objects)
main.o : main.c defs.h
cc -c main.c
kbd.o : kbd.c defs.h command.h
cc -c kbd.c
command.o : command.c defs.h command.h
cc -c command.c
display.o : display.c defs.h buffer.h
cc -c display.c
insert.o : insert.c defs.h buffer.h
cc -c insert.c
search.o : search.c defs.h buffer.h
cc -c search.c
files.o : files.c defs.h buffer.h command.h
cc -c files.c
utils.o : utils.c defs.h
cc -c utils.c
clean :
rm edit $(objects)
It is not necessary to spell out the commands for compiling the individual
C source files, because make can figure them out: it has an
implicit rule for updating a `.o' file from a correspondingly
named `.c' file using a `cc -c' command. For example, it will
use the command `cc -c main.c -o main.o' to compile `main.c' into
`main.o'. We can therefore omit the commands from the rules for the
object files. See section Using Implicit Rules.
When a `.c' file is used automatically in this way, it is also
automatically added to the list of prerequisites. We can therefore omit
the `.c' files from the prerequisites, provided we omit the commands.
Here is the entire example, with both of these changes, and a variable
objects as suggested above:
This is how we would write the makefile in actual practice. (The
complications associated with `clean' are described elsewhere.
See section Phony Targets, and section Errors in Commands.)
Because implicit rules are so convenient, they are important. You
will see them used frequently.
When the objects of a makefile are created only by implicit rules, an
alternative style of makefile is possible. In this style of makefile,
you group entries by their prerequisites instead of by their targets.
Here is what one looks like:
Here `defs.h' is given as a prerequisite of all the object files;
`command.h' and `buffer.h' are prerequisites of the specific
object files listed for them.
Whether this is better is a matter of taste: it is more compact, but some
people dislike it because they find it clearer to put all the information
about each target in one place.
Compiling a program is not the only thing you might want to write rules
for. Makefiles commonly tell how to do a few other things besides
compiling a program: for example, how to delete all the object files
and executables so that the directory is `clean'.
Here is how we
could write a make rule for cleaning our example editor:
clean:
rm edit $(objects)
In practice, we might want to write the rule in a somewhat more
complicated manner to handle unanticipated situations. We would do this:
.PHONY : clean
clean :
-rm edit $(objects)
This prevents make from getting confused by an actual file
called `clean' and causes it to continue in spite of errors from
rm. (See section Phony Targets, and section Errors in Commands.)
A rule such as this should not be placed at the beginning of the
makefile, because we do not want it to run by default! Thus, in the
example makefile, we want the rule for edit, which recompiles
the editor, to remain the default goal.
Since clean is not a prerequisite of edit, this rule will not
run at all if we give the command `make' with no arguments. In
order to make the rule run, we have to type `make clean'.
See section How to Run make.
Makefiles contain five kinds of things: explicit rules,
implicit rules, variable definitions, directives,
and comments. Rules, variables, and directives are described at
length in later chapters.
An explicit rule says when and how to remake one or more files,
called the rule's targets. It lists the other files that the targets
depend on, call the prerequisites of the target, and may also give
commands to use to create or update the targets. See section Writing Rules.
An implicit rule says when and how to remake a class of files
based on their names. It describes how a target may depend on a file
with a name similar to the target and gives commands to create or
update such a target. See section Using Implicit Rules.
A variable definition is a line that specifies a text string
value for a variable that can be substituted into the text later. The
simple makefile example shows a variable definition for objects
as a list of all object files (see section Variables Make Makefiles Simpler).
A directive is a command for make to do something special while
reading the makefile. These include:
Deciding (based on the values of variables) whether to use or
ignore a part of the makefile (see section Conditional Parts of Makefiles).
Defining a variable from a verbatim string containing multiple lines
(see section Defining Variables Verbatim).
`#' in a line of a makefile starts a comment. It and the rest of
the line are ignored, except that a trailing backslash not escaped by
another backslash will continue the comment across multiple lines.
Comments may appear on any of the lines in the makefile, except within a
define directive, and perhaps within commands (where the shell
decides what is a comment). A line containing just a comment (with
perhaps spaces before it) is effectively blank, and is ignored.
By default, when make looks for the makefile, it tries the
following names, in order: `GNUmakefile', `makefile'
and `Makefile'.
Normally you should call your makefile either `makefile' or
`Makefile'. (We recommend `Makefile' because it appears
prominently near the beginning of a directory listing, right near other
important files such as `README'.) The first name checked,
`GNUmakefile', is not recommended for most makefiles. You should
use this name if you have a makefile that is specific to GNU
make, and will not be understood by other versions of
make. Other make programs look for `makefile' and
`Makefile', but not `GNUmakefile'.
If make finds none of these names, it does not use any makefile.
Then you must specify a goal with a command argument, and make
will attempt to figure out how to remake it using only its built-in
implicit rules. See section Using Implicit Rules.
If you want to use a nonstandard name for your makefile, you can specify
the makefile name with the `-f' or `--file' option. The
arguments `-f name' or `--file=name' tell
make to read the file name as the makefile. If you use
more than one `-f' or `--file' option, you can specify several
makefiles. All the makefiles are effectively concatenated in the order
specified. The default makefile names `GNUmakefile',
`makefile' and `Makefile' are not checked automatically if you
specify `-f' or `--file'.
The include directive tells make to suspend reading the
current makefile and read one or more other makefiles before continuing.
The directive is a line in the makefile that looks like this:
include filenames...
filenames can contain shell file name patterns.
Extra spaces are allowed and ignored at the beginning of the line, but
a tab is not allowed. (If the line begins with a tab, it will be
considered a command line.) Whitespace is required between
include and the file names, and between file names; extra
whitespace is ignored there and at the end of the directive. A
comment starting with `#' is allowed at the end of the line. If
the file names contain any variable or function references, they are
expanded. See section How to Use Variables.
For example, if you have three `.mk' files, `a.mk',
`b.mk', and `c.mk', and $(bar) expands to
bish bash, then the following expression
include foo *.mk $(bar)
is equivalent to
include foo a.mk b.mk c.mk bish bash
When make processes an include directive, it suspends
reading of the containing makefile and reads from each listed file in
turn. When that is finished, make resumes reading the
makefile in which the directive appears.
One occasion for using include directives is when several programs,
handled by individual makefiles in various directories, need to use a
common set of variable definitions
(see section Setting Variables) or pattern rules
(see section Defining and Redefining Pattern Rules).
Another such occasion is when you want to generate prerequisites from
source files automatically; the prerequisites can be put in a file that
is included by the main makefile. This practice is generally cleaner
than that of somehow appending the prerequisites to the end of the main
makefile as has been traditionally done with other versions of
make. See section Generating Prerequisites Automatically.
If the specified name does not start with a slash, and the file is not
found in the current directory, several other directories are searched.
First, any directories you have specified with the `-I' or
`--include-dir' option are searched
(see section Summary of Options).
Then the following directories (if they exist)
are searched, in this order:
`prefix/include' (normally `/usr/local/include'(1))
`/usr/gnu/include',
`/usr/local/include', `/usr/include'.
If an included makefile cannot be found in any of these directories, a
warning message is generated, but it is not an immediately fatal error;
processing of the makefile containing the include continues.
Once it has finished reading makefiles, make will try to remake
any that are out of date or don't exist.
See section How Makefiles Are Remade.
Only after it has tried to find a way to remake a makefile and failed,
will make diagnose the missing makefile as a fatal error.
If you want make to simply ignore a makefile which does not exist
and cannot be remade, with no error message, use the -include
directive instead of include, like this:
-include filenames...
This is acts like include in every way except that there is no
error (not even a warning) if any of the filenames do not exist.
For compatibility with some other make implementations,
sinclude is another name for -include.
If the environment variable MAKEFILES is defined, make
considers its value as a list of names (separated by whitespace) of
additional makefiles to be read before the others. This works much like
the include directive: various directories are searched for those
files (see section Including Other Makefiles). In addition, the
default goal is never taken from one of these makefiles and it is not an
error if the files listed in MAKEFILES are not found.
The main use of MAKEFILES is in communication between recursive
invocations of make (see section Recursive Use of make). It usually is not desirable to set the environment
variable before a top-level invocation of make, because it is
usually better not to mess with a makefile from outside. However, if
you are running make without a specific makefile, a makefile in
MAKEFILES can do useful things to help the built-in implicit
rules work better, such as defining search paths (see section Searching Directories for Prerequisites).
Some users are tempted to set MAKEFILES in the environment
automatically on login, and program makefiles to expect this to be done.
This is a very bad idea, because such makefiles will fail to work if run by
anyone else. It is much better to write explicit include directives
in the makefiles. See section Including Other Makefiles.
Sometimes makefiles can be remade from other files, such as RCS or SCCS
files. If a makefile can be remade from other files, you probably want
make to get an up-to-date version of the makefile to read in.
To this end, after reading in all makefiles, make will consider
each as a goal target and attempt to update it. If a makefile has a
rule which says how to update it (found either in that very makefile or
in another one) or if an implicit rule applies to it (see section Using Implicit Rules), it will be updated if necessary. After
all makefiles have been checked, if any have actually been changed,
make starts with a clean slate and reads all the makefiles over
again. (It will also attempt to update each of them over again, but
normally this will not change them again, since they are already up to
date.)
If you know that one or more of your makefiles cannot be remade and you
want to keep make from performing an implicit rule search on
them, perhaps for efficiency reasons, you can use any normal method of
preventing implicit rule lookup to do so. For example, you can write an
explicit rule with the makefile as the target, and an empty command
string (see section Using Empty Commands).
If the makefiles specify a double-colon rule to remake a file with
commands but no prerequisites, that file will always be remade
(see section Double-Colon Rules). In the case of makefiles, a makefile that has a
double-colon rule with commands but no prerequisites will be remade every
time make is run, and then again after make starts over
and reads the makefiles in again. This would cause an infinite loop:
make would constantly remake the makefile, and never do anything
else. So, to avoid this, make will not attempt to
remake makefiles which are specified as targets of a double-colon rule
with commands but no prerequisites.
If you do not specify any makefiles to be read with `-f' or
`--file' options, make will try the default makefile names;
see section What Name to Give Your Makefile. Unlike
makefiles explicitly requested with `-f' or `--file' options,
make is not certain that these makefiles should exist. However,
if a default makefile does not exist but can be created by running
make rules, you probably want the rules to be run so that the
makefile can be used.
Therefore, if none of the default makefiles exists, make will try
to make each of them in the same order in which they are searched for
(see section What Name to Give Your Makefile)
until it succeeds in making one, or it runs out of names to try. Note
that it is not an error if make cannot find or make any makefile;
a makefile is not always necessary.
When you use the `-t' or `--touch' option
(see section Instead of Executing the Commands),
you would not want to use an out-of-date makefile to decide which
targets to touch. So the `-t' option has no effect on updating
makefiles; they are really updated even if `-t' is specified.
Likewise, `-q' (or `--question') and `-n' (or
`--just-print') do not prevent updating of makefiles, because an
out-of-date makefile would result in the wrong output for other targets.
Thus, `make -f mfile -n foo' will update `mfile', read it in,
and then print the commands to update `foo' and its prerequisites
without running them. The commands printed for `foo' will be those
specified in the updated contents of `mfile'.
However, on occasion you might actually wish to prevent updating of even
the makefiles. You can do this by specifying the makefiles as goals in
the command line as well as specifying them as makefiles. When the
makefile name is specified explicitly as a goal, the options `-t'
and so on do apply to them.
Thus, `make -f mfile -n mfile foo' would read the makefile
`mfile', print the commands needed to update it without actually
running them, and then print the commands needed to update `foo'
without running them. The commands for `foo' will be those
specified by the existing contents of `mfile'.
Sometimes it is useful to have a makefile that is mostly just like
another makefile. You can often use the `include' directive to
include one in the other, and add more targets or variable definitions.
However, if the two makefiles give different commands for the same
target, make will not let you just do this. But there is another way.
In the containing makefile (the one that wants to include the other),
you can use a match-anything pattern rule to say that to remake any
target that cannot be made from the information in the containing
makefile, make should look in another makefile.
See section Defining and Redefining Pattern Rules, for more information on pattern rules.
For example, if you have a makefile called `Makefile' that says how
to make the target `foo' (and other targets), you can write a
makefile called `GNUmakefile' that contains:
If you say `make foo', make will find `GNUmakefile',
read it, and see that to make `foo', it needs to run the command
`frobnicate > foo'. If you say `make bar', make will
find no way to make `bar' in `GNUmakefile', so it will use the
commands from the pattern rule: `make -f Makefile bar'. If
`Makefile' provides a rule for updating `bar', make
will apply the rule. And likewise for any other target that
`GNUmakefile' does not say how to make.
The way this works is that the pattern rule has a pattern of just
`%', so it matches any target whatever. The rule specifies a
prerequisite `force', to guarantee that the commands will be run even
if the target file already exists. We give `force' target empty
commands to prevent make from searching for an implicit rule to
build it--otherwise it would apply the same match-anything rule to
`force' itself and create a prerequisite loop!
GNU make does its work in two distinct phases. During the first
phase it reads all the makefiles, included makefiles, etc. and
internalizes all the variables and their values, implicit and explicit
rules, and constructs a dependency graph of all the targets and their
prerequisites. During the second phase, make uses these internal
structures to determine what targets will need to be rebuilt and to
invoke the rules necessary to do so.
It's important to understand this two-phase approach because it has a
direct impact on how variable and function expansion happens; this is
often a source of some confusion when writing makefiles. Here we will
present a summary of the phases in which expansion happens for different
constructs within the makefile. We say that expansion is
immediate if it happens during the first phase: in this case
make will expand any variables or functions in that section of a
construct as the makefile is parsed. We say that expansion is
deferred if expansion is not performed immediately. Expansion of
deferred construct is not performed until either the construct appears
later in an immediate context, or until the second phase.
You may not be familiar with some of these constructs yet. You can
reference this section as you become familiar with them, in later
chapters.
For the append operator, `+=', the right-hand side is considered
immediate if the variable was previously set as a simple variable
(`:='), and deferred otherwise.
Conditional Syntax
All instances of conditional syntax are parsed immediately, in their
entirety; this includes the ifdef, ifeq, ifndef,
and ifneq forms.
Rule Definition
A rule is always expanded the same way, regardless of the form:
immediate : immediate ; deferreddeferred
That is, the target and prerequisite sections are expanded immediately,
and the commands used to construct the target are always deferred. This
general rule is true for explicit rules, pattern rules, suffix rules,
static pattern rules, and simple prerequisite definitions.
A rule appears in the makefile and says when and how to remake
certain files, called the rule's targets (most often only one per rule).
It lists the other files that are the prerequisites of the target, and
commands to use to create or update the target.
The order of rules is not significant, except for determining the
default goal: the target for make to consider, if you do
not otherwise specify one. The default goal is the target of the first
rule in the first makefile. If the first rule has multiple targets,
only the first target is taken as the default. There are two
exceptions: a target starting with a period is not a default unless it
contains one or more slashes, `/', as well; and, a target that
defines a pattern rule has no effect on the default goal.
(See section Defining and Redefining Pattern Rules.)
Therefore, we usually write the makefile so that the first rule is the
one for compiling the entire program or all the programs described by
the makefile (often with a target called `all').
See section Arguments to Specify the Goals.
The targets are file names, separated by spaces. Wildcard
characters may be used (see section Using Wildcard Characters in File Names) and a name of the form `a(m)'
represents member m in archive file a
(see section Archive Members as Targets).
Usually there is only one
target per rule, but occasionally there is a reason to have more
(see section Multiple Targets in a Rule).
The command lines start with a tab character. The first command may
appear on the line after the prerequisites, with a tab character, or may
appear on the same line, with a semicolon. Either way, the effect is the
same. See section Writing the Commands in Rules.
Because dollar signs are used to start variable references, if you really
want a dollar sign in a rule you must write two of them, `$$'
(see section How to Use Variables).
You may split a long line by inserting a backslash
followed by a newline, but this is not required, as make places no
limit on the length of a line in a makefile.
A rule tells make two things: when the targets are out of date,
and how to update them when necessary.
The criterion for being out of date is specified in terms of the
prerequisites, which consist of file names separated by spaces.
(Wildcards and archive members (see section Using make to Update Archive Files) are allowed here too.)
A target is out of date if it does not exist or if it is older than any
of the prerequisites (by comparison of last-modification times). The
idea is that the contents of the target file are computed based on
information in the prerequisites, so if any of the prerequisites changes,
the contents of the existing target file are no longer necessarily
valid.
How to update is specified by commands. These are lines to be
executed by the shell (normally `sh'), but with some extra features
(see section Writing the Commands in Rules).
A single file name can specify many files using wildcard characters.
The wildcard characters in make are `*', `?' and
`[...]', the same as in the Bourne shell. For example, `*.c'
specifies a list of all the files (in the working directory) whose names
end in `.c'.
The character `~' at the beginning of a file name also has special
significance. If alone, or followed by a slash, it represents your home
directory. For example `~/bin' expands to `/home/you/bin'.
If the `~' is followed by a word, the string represents the home
directory of the user named by that word. For example `~john/bin'
expands to `/home/john/bin'. On systems which don't have a home
directory for each user (such as MS-DOS or MS-Windows), this
functionality can be simulated by setting the environment variable
HOME.
Wildcard expansion happens automatically in targets, in prerequisites,
and in commands (where the shell does the expansion). In other
contexts, wildcard expansion happens only if you request it explicitly
with the wildcard function.
The special significance of a wildcard character can be turned off by
preceding it with a backslash. Thus, `foo\*bar' would refer to a
specific file whose name consists of `foo', an asterisk, and
`bar'.
Wildcards can be used in the commands of a rule, where they are expanded
by the shell. For example, here is a rule to delete all the object files:
clean:
rm -f *.o
Wildcards are also useful in the prerequisites of a rule. With the
following rule in the makefile, `make print' will print all the
`.c' files that have changed since the last time you printed them:
Wildcard expansion does not happen when you define a variable. Thus, if
you write this:
objects = *.o
then the value of the variable objects is the actual string
`*.o'. However, if you use the value of objects in a target,
prerequisite or command, wildcard expansion will take place at that time.
To set objects to the expansion, instead use:
Now here is an example of a naive way of using wildcard expansion, that
does not do what you would intend. Suppose you would like to say that the
executable file `foo' is made from all the object files in the
directory, and you write this:
The value of objects is the actual string `*.o'. Wildcard
expansion happens in the rule for `foo', so that each existing`.o' file becomes a prerequisite of `foo' and will be recompiled if
necessary.
But what if you delete all the `.o' files? When a wildcard matches
no files, it is left as it is, so then `foo' will depend on the
oddly-named file `*.o'. Since no such file is likely to exist,
make will give you an error saying it cannot figure out how to
make `*.o'. This is not what you want!
Actually it is possible to obtain the desired result with wildcard
expansion, but you need more sophisticated techniques, including the
wildcard function and string substitution.
These are described in the following section.
Microsoft operating systems (MS-DOS and MS-Windows) use backslashes to
separate directories in pathnames, like so:
c:\foo\bar\baz.c
This is equivalent to the Unix-style `c:/foo/bar/baz.c' (the
`c:' part is the so-called drive letter). When make runs on
these systems, it supports backslashes as well as the Unix-style forward
slashes in pathnames. However, this support does not include the
wildcard expansion, where backslash is a quote character. Therefore,
you must use Unix-style slashes in these cases.
Wildcard expansion happens automatically in rules. But wildcard expansion
does not normally take place when a variable is set, or inside the
arguments of a function. If you want to do wildcard expansion in such
places, you need to use the wildcard function, like this:
$(wildcard pattern...)
This string, used anywhere in a makefile, is replaced by a
space-separated list of names of existing files that match one of the
given file name patterns. If no existing file name matches a pattern,
then that pattern is omitted from the output of the wildcard
function. Note that this is different from how unmatched wildcards
behave in rules, where they are used verbatim rather than ignored
(see section Pitfalls of Using Wildcards).
One use of the wildcard function is to get a list of all the C source
files in a directory, like this:
$(wildcard *.c)
We can change the list of C source files into a list of object files by
replacing the `.c' suffix with `.o' in the result, like this:
(This takes advantage of the implicit rule for compiling C programs, so
there is no need to write explicit rules for compiling the files.
See section The Two Flavors of Variables, for an explanation of
`:=', which is a variant of `='.)
For large systems, it is often desirable to put sources in a separate
directory from the binaries. The directory search features of
make facilitate this by searching several directories
automatically to find a prerequisite. When you redistribute the files
among directories, you do not need to change the individual rules,
just the search paths.
The value of the make variable VPATH specifies a list of
directories that make should search. Most often, the
directories are expected to contain prerequisite files that are not in the
current directory; however, VPATH specifies a search list that
make applies for all files, including files which are targets of
rules.
Thus, if a file that is listed as a target or prerequisite does not exist
in the current directory, make searches the directories listed in
VPATH for a file with that name. If a file is found in one of
them, that file may become the prerequisite (see below). Rules may then
specify the names of files in the prerequisite list as if they all
existed in the current directory. See section Writing Shell Commands with Directory Search.
In the VPATH variable, directory names are separated by colons or
blanks. The order in which directories are listed is the order followed
by make in its search. (On MS-DOS and MS-Windows, semi-colons
are used as separators of directory names in VPATH, since the
colon can be used in the pathname itself, after the drive letter.)
For example,
VPATH = src:../headers
specifies a path containing two directories, `src' and
`../headers', which make searches in that order.
With this value of VPATH, the following rule,
foo.o : foo.c
is interpreted as if it were written like this:
foo.o : src/foo.c
assuming the file `foo.c' does not exist in the current directory but
is found in the directory `src'.
Similar to the VPATH variable, but more selective, is the
vpath directive (note lower case), which allows you to specify a
search path for a particular class of file names: those that match a
particular pattern. Thus you can supply certain search directories for
one class of file names and other directories (or none) for other file
names.
There are three forms of the vpath directive:
vpath patterndirectories
Specify the search path directories for file names that match
pattern.
The search path, directories, is a list of directories to be
searched, separated by colons (semi-colons on MS-DOS and MS-Windows) or
blanks, just like the search path used in the VPATH variable.
vpath pattern
Clear out the search path associated with pattern.
vpath
Clear all search paths previously specified with vpath directives.
A vpath pattern is a string containing a `%' character. The
string must match the file name of a prerequisite that is being searched
for, the `%' character matching any sequence of zero or more
characters (as in pattern rules; see section Defining and Redefining Pattern Rules). For example, %.h matches files that
end in .h. (If there is no `%', the pattern must match the
prerequisite exactly, which is not useful very often.)
`%' characters in a vpath directive's pattern can be quoted
with preceding backslashes (`\'). Backslashes that would otherwise
quote `%' characters can be quoted with more backslashes.
Backslashes that quote `%' characters or other backslashes are
removed from the pattern before it is compared to file names. Backslashes
that are not in danger of quoting `%' characters go unmolested.
When a prerequisite fails to exist in the current directory, if the
pattern in a vpath directive matches the name of the
prerequisite file, then the directories in that directive are searched
just like (and before) the directories in the VPATH variable.
For example,
vpath %.h ../headers
tells make to look for any prerequisite whose name ends in `.h'
in the directory `../headers' if the file is not found in the current
directory.
If several vpath patterns match the prerequisite file's name, then
make processes each matching vpath directive one by one,
searching all the directories mentioned in each directive. make
handles multiple vpath directives in the order in which they
appear in the makefile; multiple directives with the same pattern are
independent of each other.
Thus,
vpath %.c foo
vpath % blish
vpath %.c bar
will look for a file ending in `.c' in `foo', then
`blish', then `bar', while
vpath %.c foo:bar
vpath % blish
will look for a file ending in `.c' in `foo', then
`bar', then `blish'.
When a prerequisite is found through directory search, regardless of type
(general or selective), the pathname located may not be the one that
make actually provides you in the prerequisite list. Sometimes
the path discovered through directory search is thrown away.
The algorithm make uses to decide whether to keep or abandon a
path found via directory search is as follows:
If a target file does not exist at the path specified in the makefile,
directory search is performed.
If the directory search is successful, that path is kept and this file
is tentatively stored as the target.
All prerequisites of this target are examined using this same method.
After processing the prerequisites, the target may or may not need to be
rebuilt:
If the target does not need to be rebuilt, the path to the file
found during directory search is used for any prerequisite lists which
contain this target. In short, if make doesn't need to rebuild
the target then you use the path found via directory search.
If the target does need to be rebuilt (is out-of-date), the
pathname found during directory search is thrown away, and the
target is rebuilt using the file name specified in the makefile. In
short, if make must rebuild, then the target is rebuilt locally,
not in the directory found via directory search.
This algorithm may seem complex, but in practice it is quite often
exactly what you want.
Other versions of make use a simpler algorithm: if the file does
not exist, and it is found via directory search, then that pathname is
always used whether or not the target needs to be built. Thus, if the
target is rebuilt it is created at the pathname discovered during
directory search.
If, in fact, this is the behavior you want for some or all of your
directories, you can use the GPATH variable to indicate this to
make.
GPATH has the same syntax and format as VPATH (that is, a
space- or colon-delimited list of pathnames). If an out-of-date target
is found by directory search in a directory that also appears in
GPATH, then that pathname is not thrown away. The target is
rebuilt using the expanded path.
When a prerequisite is found in another directory through directory search,
this cannot change the commands of the rule; they will execute as written.
Therefore, you must write the commands with care so that they will look for
the prerequisite in the directory where make finds it.
This is done with the automatic variables such as `$^'
(see section Automatic Variables).
For instance, the value of `$^' is a
list of all the prerequisites of the rule, including the names of
the directories in which they were found, and the value of
`$@' is the target. Thus:
foo.o : foo.c
cc -c $(CFLAGS) $^ -o $@
(The variable CFLAGS exists so you can specify flags for C
compilation by implicit rules; we use it here for consistency so it will
affect all C compilations uniformly;
see section Variables Used by Implicit Rules.)
Often the prerequisites include header files as well, which you do not
want to mention in the commands. The automatic variable `$<' is
just the first prerequisite:
The search through the directories specified in VPATH or with
vpath also happens during consideration of implicit rules
(see section Using Implicit Rules).
For example, when a file `foo.o' has no explicit rule, make
considers implicit rules, such as the built-in rule to compile
`foo.c' if that file exists. If such a file is lacking in the
current directory, the appropriate directories are searched for it. If
`foo.c' exists (or is mentioned in the makefile) in any of the
directories, the implicit rule for C compilation is applied.
The commands of implicit rules normally use automatic variables as a
matter of necessity; consequently they will use the file names found by
directory search with no extra effort.
Directory search applies in a special way to libraries used with the
linker. This special feature comes into play when you write a prerequisite
whose name is of the form `-lname'. (You can tell something
strange is going on here because the prerequisite is normally the name of a
file, and the file name of a library generally looks like
`libname.a', not like `-lname'.)
When a prerequisite's name has the form `-lname', make
handles it specially by searching for the file `libname.so' in
the current directory, in directories specified by matching vpath
search paths and the VPATH search path, and then in the
directories `/lib', `/usr/lib', and `prefix/lib'
(normally `/usr/local/lib', but MS-DOS/MS-Windows versions of
make behave as if prefix is defined to be the root of the
DJGPP installation tree).
If that file is not found, then the file `libname.a' is
searched for, in the same directories as above.
For example, if there is a `/usr/lib/libcurses.a' library on your
system (and no `/usr/lib/libcurses.so' file), then
foo : foo.c -lcurses
cc $^ -o $@
would cause the command `cc foo.c /usr/lib/libcurses.a -o foo' to
be executed when `foo' is older than `foo.c' or than
`/usr/lib/libcurses.a'.
Although the default set of files to be searched for is
`libname.so' and `libname.a', this is customizable
via the .LIBPATTERNS variable. Each word in the value of this
variable is a pattern string. When a prerequisite like
`-lname' is seen, make will replace the percent in
each pattern in the list with name and perform the above directory
searches using that library filename. If no library is found, the next
word in the list will be used.
The default value for .LIBPATTERNS is "`lib%.so lib%.a'",
which provides the default behavior described above.
You can turn off link library expansion completely by setting this
variable to an empty value.
A phony target is one that is not really the name of a file. It is just a
name for some commands to be executed when you make an explicit request.
There are two reasons to use a phony target: to avoid a conflict with
a file of the same name, and to improve performance.
If you write a rule whose commands will not create the target file, the
commands will be executed every time the target comes up for remaking.
Here is an example:
clean:
rm *.o temp
Because the rm command does not create a file named `clean',
probably no such file will ever exist. Therefore, the rm command
will be executed every time you say `make clean'.
The phony target will cease to work if anything ever does create a file
named `clean' in this directory. Since it has no prerequisites, the
file `clean' would inevitably be considered up to date, and its
commands would not be executed. To avoid this problem, you can explicitly
declare the target to be phony, using the special target .PHONY
(see section Special Built-in Target Names) as follows:
.PHONY : clean
Once this is done, `make clean' will run the commands regardless of
whether there is a file named `clean'.
Since it knows that phony targets do not name actual files that could be
remade from other files, make skips the implicit rule search for
phony targets (see section Using Implicit Rules). This is why declaring a target
phony is good for performance, even if you are not worried about the
actual file existing.
Thus, you first write the line that states that clean is a
phony target, then you write the rule, like this:
.PHONY: clean
clean:
rm *.o temp
Another example of the usefulness of phony targets is in conjunction
with recursive invocations of make. In this case the makefile
will often contain a variable which lists a number of subdirectories to
be built. One way to handle this is with one rule whose command is a
shell loop over the subdirectories, like this:
SUBDIRS = foo bar baz
subdirs:
for dir in $(SUBDIRS); do \
$(MAKE) -C $$dir; \
done
There are a few of problems with this method, however. First, any error
detected in a submake is not noted by this rule, so it will continue to
build the rest of the directories even when one fails. This can be
overcome by adding shell commands to note the error and exit, but then
it will do so even if make is invoked with the -k option,
which is unfortunate. Second, and perhaps more importantly, you cannot
take advantage of the parallel build capabilities of make using this
method, since there is only one rule.
By declaring the subdirectories as phony targets (you must do this as
the subdirectory obviously always exists; otherwise it won't be built)
you can remove these problems:
Here we've also declared that the `foo' subdirectory cannot be
built until after the `baz' subdirectory is complete; this kind of
relationship declaration is particularly important when attempting
parallel builds.
A phony target should not be a prerequisite of a real target file; if it
is, its commands are run every time make goes to update that
file. As long as a phony target is never a prerequisite of a real
target, the phony target commands will be executed only when the phony
target is a specified goal (see section Arguments to Specify the Goals).
Phony targets can have prerequisites. When one directory contains multiple
programs, it is most convenient to describe all of the programs in one
makefile `./Makefile'. Since the target remade by default will be the
first one in the makefile, it is common to make this a phony target named
`all' and give it, as prerequisites, all the individual programs. For
example:
all : prog1 prog2 prog3
.PHONY : all
prog1 : prog1.o utils.o
cc -o prog1 prog1.o utils.o
prog2 : prog2.o
cc -o prog2 prog2.o
prog3 : prog3.o sort.o utils.o
cc -o prog3 prog3.o sort.o utils.o
Now you can say just `make' to remake all three programs, or specify
as arguments the ones to remake (as in `make prog1 prog3').
When one phony target is a prerequisite of another, it serves as a subroutine
of the other. For example, here `make cleanall' will delete the
object files, the difference files, and the file `program':
If a rule has no prerequisites or commands, and the target of the rule
is a nonexistent file, then make imagines this target to have
been updated whenever its rule is run. This implies that all targets
depending on this one will always have their commands run.
An example will illustrate this:
clean: FORCE
rm $(objects)
FORCE:
Here the target `FORCE' satisfies the special conditions, so the
target `clean' that depends on it is forced to run its commands.
There is nothing special about the name `FORCE', but that is one name
commonly used this way.
As you can see, using `FORCE' this way has the same results as using
`.PHONY: clean'.
Using `.PHONY' is more explicit and more efficient. However,
other versions of make do not support `.PHONY'; thus
`FORCE' appears in many makefiles. See section Phony Targets.
The empty target is a variant of the phony target; it is used to hold
commands for an action that you request explicitly from time to time.
Unlike a phony target, this target file can really exist; but the file's
contents do not matter, and usually are empty.
The purpose of the empty target file is to record, with its
last-modification time, when the rule's commands were last executed. It
does so because one of the commands is a touch command to update the
target file.
The empty target file should have some prerequisites (otherwise it
doesn't make sense). When you ask to remake the empty target, the
commands are executed if any prerequisite is more recent than the target;
in other words, if a prerequisite has changed since the last time you
remade the target. Here is an example:
print: foo.c bar.c
lpr -p $?
touch print
With this rule, `make print' will execute the lpr command if
either source file has changed since the last `make print'. The
automatic variable `$?' is used to print only those files that have
changed (see section Automatic Variables).
Certain names have special meanings if they appear as targets.
.PHONY
The prerequisites of the special target .PHONY are considered to
be phony targets. When it is time to consider such a target,
make will run its commands unconditionally, regardless of
whether a file with that name exists or what its last-modification
time is. See section Phony Targets.
.SUFFIXES
The prerequisites of the special target .SUFFIXES are the list
of suffixes to be used in checking for suffix rules.
See section Old-Fashioned Suffix Rules.
.DEFAULT
The commands specified for .DEFAULT are used for any target for
which no rules are found (either explicit rules or implicit rules).
See section Defining Last-Resort Default Rules. If .DEFAULT commands are specified, every
file mentioned as a prerequisite, but not as a target in a rule, will have
these commands executed on its behalf. See section Implicit Rule Search Algorithm.
.PRECIOUS
The targets which .PRECIOUS depends on are given the following
special treatment: if make is killed or interrupted during the
execution of their commands, the target is not deleted.
See section Interrupting or Killing make. Also, if the
target is an intermediate file, it will not be deleted after it is no
longer needed, as is normally done. See section Chains of Implicit Rules. In this latter respect it overlaps with the
.SECONDARY special target.
You can also list the target pattern of an implicit rule (such as
`%.o') as a prerequisite file of the special target .PRECIOUS
to preserve intermediate files created by rules whose target patterns
match that file's name.
.INTERMEDIATE
The targets which .INTERMEDIATE depends on are treated as
intermediate files. See section Chains of Implicit Rules.
.INTERMEDIATE with no prerequisites has no effect.
.SECONDARY
The targets which .SECONDARY depends on are treated as
intermediate files, except that they are never automatically deleted.
See section Chains of Implicit Rules.
.SECONDARY with no prerequisites causes all targets to be treated
as secondary (i.e., no target is removed because it is considered
intermediate).
.DELETE_ON_ERROR
If .DELETE_ON_ERROR is mentioned as a target anywhere in the
makefile, then make will delete the target of a rule if it has
changed and its commands exit with a nonzero exit status, just as it
does when it receives a signal. See section Errors in Commands.
.IGNORE
If you specify prerequisites for .IGNORE, then make will
ignore errors in execution of the commands run for those particular
files. The commands for .IGNORE are not meaningful.
If mentioned as a target with no prerequisites, .IGNORE says to
ignore errors in execution of commands for all files. This usage of
`.IGNORE' is supported only for historical compatibility. Since
this affects every command in the makefile, it is not very useful; we
recommend you use the more selective ways to ignore errors in specific
commands. See section Errors in Commands.
.SILENT
If you specify prerequisites for .SILENT, then make will
not print the commands to remake those particular files before executing
them. The commands for .SILENT are not meaningful.
If mentioned as a target with no prerequisites, .SILENT says not
to print any commands before executing them. This usage of
`.SILENT' is supported only for historical compatibility. We
recommend you use the more selective ways to silence specific commands.
See section Command Echoing. If you want to silence all commands
for a particular run of make, use the `-s' or
`--silent' option (see section Summary of Options).
.EXPORT_ALL_VARIABLES
Simply by being mentioned as a target, this tells make to
export all variables to child processes by default.
See section Communicating Variables to a Sub-make.
.NOTPARALLEL
If .NOTPARALLEL is mentioned as a target, then this invocation of
make will be run serially, even if the `-j' option is
given. Any recursively invoked make command will still be run in
parallel (unless its makefile contains this target). Any prerequisites
on this target are ignored.
Any defined implicit rule suffix also counts as a special target if it
appears as a target, and so does the concatenation of two suffixes, such
as `.c.o'. These targets are suffix rules, an obsolete way of
defining implicit rules (but a way still widely used). In principle, any
target name could be special in this way if you break it in two and add
both pieces to the suffix list. In practice, suffixes normally begin with
`.', so these special target names also begin with `.'.
See section Old-Fashioned Suffix Rules.
A rule with multiple targets is equivalent to writing many rules, each with
one target, and all identical aside from that. The same commands apply to
all the targets, but their effects may vary because you can substitute the
actual target name into the command using `$@'. The rule contributes
the same prerequisites to all the targets also.
This is useful in two cases.
You want just prerequisites, no commands. For example:
kbd.o command.o files.o: command.h
gives an additional prerequisite to each of the three object files
mentioned.
Similar commands work for all the targets. The commands do not need
to be absolutely identical, since the automatic variable `$@'
can be used to substitute the particular target to be remade into the
commands (see section Automatic Variables). For example:
Here we assume the hypothetical program generate makes two
types of output, one if given `-big' and one if given
`-little'.
See section Functions for String Substitution and Analysis,
for an explanation of the subst function.
Suppose you would like to vary the prerequisites according to the target,
much as the variable `$@' allows you to vary the commands.
You cannot do this with multiple targets in an ordinary rule, but you can
do it with a static pattern rule.
See section Static Pattern Rules.
One file can be the target of several rules. All the prerequisites
mentioned in all the rules are merged into one list of prerequisites for
the target. If the target is older than any prerequisite from any rule,
the commands are executed.
There can only be one set of commands to be executed for a file.
If more than one rule gives commands for the same file,
make uses the last set given and prints an error message.
(As a special case, if the file's name begins with a dot, no
error message is printed. This odd behavior is only for
compatibility with other implementations of make.)
There is no reason to
write your makefiles this way; that is why make gives you
an error message.
An extra rule with just prerequisites can be used to give a few extra
prerequisites to many files at once. For example, one usually has a
variable named objects containing a list of all the compiler output
files in the system being made. An easy way to say that all of them must
be recompiled if `config.h' changes is to write the following:
This could be inserted or taken out without changing the rules that really
specify how to make the object files, making it a convenient form to use if
you wish to add the additional prerequisite intermittently.
Another wrinkle is that the additional prerequisites could be specified with
a variable that you set with a command argument to make
(see section Overriding Variables). For example,
extradeps=
$(objects) : $(extradeps)
means that the command `make extradeps=foo.h' will consider
`foo.h' as a prerequisite of each object file, but plain `make'
will not.
If none of the explicit rules for a target has commands, then make
searches for an applicable implicit rule to find some commands
see section Using Implicit Rules).
Static pattern rules are rules which specify multiple targets and
construct the prerequisite names for each target based on the target name.
They are more general than ordinary rules with multiple targets because the
targets do not have to have identical prerequisites. Their prerequisites must
be analogous, but not necessarily identical.
The targets list specifies the targets that the rule applies to.
The targets can contain wildcard characters, just like the targets of
ordinary rules (see section Using Wildcard Characters in File Names).
The target-pattern and dep-patterns say how to compute the
prerequisites of each target. Each target is matched against the
target-pattern to extract a part of the target name, called the
stem. This stem is substituted into each of the dep-patterns
to make the prerequisite names (one from each dep-pattern).
Each pattern normally contains the character `%' just once. When the
target-pattern matches a target, the `%' can match any part of
the target name; this part is called the stem. The rest of the
pattern must match exactly. For example, the target `foo.o' matches
the pattern `%.o', with `foo' as the stem. The targets
`foo.c' and `foo.out' do not match that pattern.
The prerequisite names for each target are made by substituting the stem
for the `%' in each prerequisite pattern. For example, if one
prerequisite pattern is `%.c', then substitution of the stem
`foo' gives the prerequisite name `foo.c'. It is legitimate
to write a prerequisite pattern that does not contain `%'; then this
prerequisite is the same for all targets.
`%' characters in pattern rules can be quoted with preceding
backslashes (`\'). Backslashes that would otherwise quote `%'
characters can be quoted with more backslashes. Backslashes that quote
`%' characters or other backslashes are removed from the pattern
before it is compared to file names or has a stem substituted into it.
Backslashes that are not in danger of quoting `%' characters go
unmolested. For example, the pattern `the\%weird\\%pattern\\' has
`the%weird\' preceding the operative `%' character, and
`pattern\\' following it. The final two backslashes are left alone
because they cannot affect any `%' character.
Here is an example, which compiles each of `foo.o' and `bar.o'
from the corresponding `.c' file:
Here `$<' is the automatic variable that holds the name of the
prerequisite and `$@' is the automatic variable that holds the name
of the target; see section Automatic Variables.
Each target specified must match the target pattern; a warning is issued
for each target that does not. If you have a list of files, only some of
which will match the pattern, you can use the filter function to
remove nonmatching file names (see section Functions for String Substitution and Analysis):
In this example the result of `$(filter %.o,$(files))' is
`bar.o lose.o', and the first static pattern rule causes each of
these object files to be updated by compiling the corresponding C source
file. The result of `$(filter %.elc,$(files))' is
`foo.elc', so that file is made from `foo.el'.
Another example shows how to use $* in static pattern rules:
A static pattern rule has much in common with an implicit rule defined as a
pattern rule (see section Defining and Redefining Pattern Rules).
Both have a pattern for the target and patterns for constructing the
names of prerequisites. The difference is in how make decides
when the rule applies.
An implicit rule can apply to any target that matches its pattern,
but it does apply only when the target has no commands otherwise
specified, and only when the prerequisites can be found. If more than one
implicit rule appears applicable, only one applies; the choice depends on
the order of rules.
By contrast, a static pattern rule applies to the precise list of targets
that you specify in the rule. It cannot apply to any other target and it
invariably does apply to each of the targets specified. If two conflicting
rules apply, and both have commands, that's an error.
The static pattern rule can be better than an implicit rule for these
reasons:
You may wish to override the usual implicit rule for a few
files whose names cannot be categorized syntactically but
can be given in an explicit list.
If you cannot be sure of the precise contents of the directories
you are using, you may not be sure which other irrelevant files
might lead make to use the wrong implicit rule. The choice
might depend on the order in which the implicit rule search is done.
With static pattern rules, there is no uncertainty: each rule applies
to precisely the targets specified.
Double-colon rules are rules written with `::' instead of
`:' after the target names. They are handled differently from
ordinary rules when the same target appears in more than one rule.
When a target appears in multiple rules, all the rules must be the same
type: all ordinary, or all double-colon. If they are double-colon, each of
them is independent of the others. Each double-colon rule's commands are
executed if the target is older than any prerequisites of that rule. This
can result in executing none, any, or all of the double-colon rules.
Double-colon rules with the same target are in fact completely separate
from one another. Each double-colon rule is processed individually, just
as rules with different targets are processed.
The double-colon rules for a target are executed in the order they appear
in the makefile. However, the cases where double-colon rules really make
sense are those where the order of executing the commands would not matter.
Double-colon rules are somewhat obscure and not often very useful; they
provide a mechanism for cases in which the method used to update a target
differs depending on which prerequisite files caused the update, and such
cases are rare.
Each double-colon rule should specify commands; if it does not, an
implicit rule will be used if one applies.
See section Using Implicit Rules.
In the makefile for a program, many of the rules you need to write often
say only that some object file depends on some header
file. For example, if `main.c' uses `defs.h' via an
#include, you would write:
main.o: defs.h
You need this rule so that make knows that it must remake
`main.o' whenever `defs.h' changes. You can see that for a
large program you would have to write dozens of such rules in your
makefile. And, you must always be very careful to update the makefile
every time you add or remove an #include.
To avoid this hassle, most modern C compilers can write these rules for
you, by looking at the #include lines in the source files.
Usually this is done with the `-M' option to the compiler.
For example, the command:
cc -M main.c
generates the output:
main.o : main.c defs.h
Thus you no longer have to write all those rules yourself.
The compiler will do it for you.
Note that such a prerequisite constitutes mentioning `main.o' in a
makefile, so it can never be considered an intermediate file by implicit
rule search. This means that make won't ever remove the file
after using it; see section Chains of Implicit Rules.
With old make programs, it was traditional practice to use this
compiler feature to generate prerequisites on demand with a command like
`make depend'. That command would create a file `depend'
containing all the automatically-generated prerequisites; then the
makefile could use include to read them in (see section Including Other Makefiles).
In GNU make, the feature of remaking makefiles makes this
practice obsolete--you need never tell make explicitly to
regenerate the prerequisites, because it always regenerates any makefile
that is out of date. See section How Makefiles Are Remade.
The practice we recommend for automatic prerequisite generation is to have
one makefile corresponding to each source file. For each source file
`name.c' there is a makefile `name.d' which lists
what files the object file `name.o' depends on. That way
only the source files that have changed need to be rescanned to produce
the new prerequisites.
Here is the pattern rule to generate a file of prerequisites (i.e., a makefile)
called `name.d' from a C source file called `name.c':
See section Defining and Redefining Pattern Rules, for information on defining pattern rules. The
`-e' flag to the shell makes it exit immediately if the
$(CC) command fails (exits with a nonzero status). Normally the
shell exits with the status of the last command in the pipeline
(sed in this case), so make would not notice a nonzero
status from the compiler.
With the GNU C compiler, you may wish to use the `-MM' flag instead
of `-M'. This omits prerequisites on system header files.
See section `Options Controlling the Preprocessor' in Using GNU CC, for details.
The purpose of the sed command is to translate (for example):
main.o : main.c defs.h
into:
main.o main.d : main.c defs.h
This makes each `.d' file depend on all the source and header files
that the corresponding `.o' file depends on. make then
knows it must regenerate the prerequisites whenever any of the source or
header files changes.
Once you've defined the rule to remake the `.d' files,
you then use the include directive to read them all in.
See section Including Other Makefiles. For example:
sources = foo.c bar.c
include $(sources:.c=.d)
(This example uses a substitution variable reference to translate the
list of source files `foo.c bar.c' into a list of prerequisite
makefiles, `foo.d bar.d'. See section Substitution References, for full
information on substitution references.) Since the `.d' files are
makefiles like any others, make will remake them as necessary
with no further work from you. See section How Makefiles Are Remade.
The commands of a rule consist of shell command lines to be executed one
by one. Each command line must start with a tab, except that the first
command line may be attached to the target-and-prerequisites line with a
semicolon in between. Blank lines and lines of just comments may appear
among the command lines; they are ignored. (But beware, an apparently
"blank" line that begins with a tab is not blank! It is an
empty command; see section Using Empty Commands.)
Users use many different shell programs, but commands in makefiles are
always interpreted by `/bin/sh' unless the makefile specifies
otherwise. See section Command Execution.
The shell that is in use determines whether comments can be written on
command lines, and what syntax they use. When the shell is
`/bin/sh', a `#' starts a comment that extends to the end of
the line. The `#' does not have to be at the beginning of a line.
Text on a line before a `#' is not part of the comment.
Normally make prints each command line before it is executed.
We call this echoing because it gives the appearance that you
are typing the commands yourself.
When a line starts with `@', the echoing of that line is suppressed.
The `@' is discarded before the command is passed to the shell.
Typically you would use this for a command whose only effect is to print
something, such as an echo command to indicate progress through
the makefile:
@echo About to make distribution files
When make is given the flag `-n' or `--just-print'
it only echoes commands, it won't execute them. See section Summary of Options. In this case and only this case, even the
commands starting with `@' are printed. This flag is useful for
finding out which commands make thinks are necessary without
actually doing them.
The `-s' or `--silent'
flag to make prevents all echoing, as if all commands
started with `@'. A rule in the makefile for the special target
.SILENT without prerequisites has the same effect
(see section Special Built-in Target Names).
.SILENT is essentially obsolete since `@' is more flexible.
When it is time to execute commands to update a target, they are executed
by making a new subshell for each line. (In practice, make may
take shortcuts that do not affect the results.)
Please note: this implies that shell commands such as cd
that set variables local to each process will not affect the following
command lines. (2) If you want to use cd
to affect the next command, put the two on a single line with a
semicolon between them. Then make will consider them a single
command and pass them, together, to a shell which will execute them in
sequence. For example:
foo : bar/lose
cd bar; gobble lose > ../foo
If you would like to split a single shell command into multiple lines of
text, you must use a backslash at the end of all but the last subline.
Such a sequence of lines is combined into a single line, by deleting the
backslash-newline sequences, before passing it to the shell. Thus, the
following is equivalent to the preceding example:
foo : bar/lose
cd bar; \
gobble lose > ../foo
The program used as the shell is taken from the variable SHELL.
By default, the program `/bin/sh' is used.
On MS-DOS, if SHELL is not set, the value of the variable
COMSPEC (which is always set) is used instead.
The processing of lines that set the variable SHELL in Makefiles
is different on MS-DOS. The stock shell, `command.com', is
ridiculously limited in its functionality and many users of make
tend to install a replacement shell. Therefore, on MS-DOS, make
examines the value of SHELL, and changes its behavior based on
whether it points to a Unix-style or DOS-style shell. This allows
reasonable functionality even if SHELL points to
`command.com'.
If SHELL points to a Unix-style shell, make on MS-DOS
additionally checks whether that shell can indeed be found; if not, it
ignores the line that sets SHELL. In MS-DOS, GNU make
searches for the shell in the following places:
In the precise place pointed to by the value of SHELL. For
example, if the makefile specifies `SHELL = /bin/sh', make
will look in the directory `/bin' on the current drive.
In the current directory.
In each of the directories in the PATH variable, in order.
In every directory it examines, make will first look for the
specific file (`sh' in the example above). If this is not found,
it will also look in that directory for that file with one of the known
extensions which identify executable files. For example `.exe',
`.com', `.bat', `.btm', `.sh', and some others.
If any of these attempts is successful, the value of SHELL will
be set to the full pathname of the shell as found. However, if none of
these is found, the value of SHELL will not be changed, and thus
the line that sets it will be effectively ignored. This is so
make will only support features specific to a Unix-style shell if
such a shell is actually installed on the system where make runs.
Note that this extended search for the shell is limited to the cases
where SHELL is set from the Makefile; if it is set in the
environment or command line, you are expected to set it to the full
pathname of the shell, exactly as things are on Unix.
The effect of the above DOS-specific processing is that a Makefile that
says `SHELL = /bin/sh' (as many Unix makefiles do), will work
on MS-DOS unaltered if you have e.g. `sh.exe' installed in some
directory along your PATH.
Unlike most variables, the variable SHELL is never set from the
environment. This is because the SHELL environment variable is
used to specify your personal choice of shell program for interactive
use. It would be very bad for personal choices like this to affect the
functioning of makefiles. See section Variables from the Environment. However, on MS-DOS and MS-Windows the value of
SHELL in the environment is used, since on those systems
most users do not set this variable, and therefore it is most likely set
specifically to be used by make. On MS-DOS, if the setting of
SHELL is not suitable for make, you can set the variable
MAKESHELL to the shell that make should use; this will
override the value of SHELL.
GNU make knows how to execute several commands at once.
Normally, make will execute only one command at a time, waiting
for it to finish before executing the next. However, the `-j' or
`--jobs' option tells make to execute many commands
simultaneously.
On MS-DOS, the `-j' option has no effect, since that system doesn't
support multi-processing.
If the `-j' option is followed by an integer, this is the number of
commands to execute at once; this is called the number of job slots.
If there is nothing looking like an integer after the `-j' option,
there is no limit on the number of job slots. The default number of job
slots is one, which means serial execution (one thing at a time).
One unpleasant consequence of running several commands simultaneously is
that output generated by the commands appears whenever each command
sends it, so messages from different commands may be interspersed.
Another problem is that two processes cannot both take input from the
same device; so to make sure that only one command tries to take input
from the terminal at once, make will invalidate the standard
input streams of all but one running command. This means that
attempting to read from standard input will usually be a fatal error (a
`Broken pipe' signal) for most child processes if there are
several.
It is unpredictable which command will have a valid standard input stream
(which will come from the terminal, or wherever you redirect the standard
input of make). The first command run will always get it first, and
the first command started after that one finishes will get it next, and so
on.
We will change how this aspect of make works if we find a better
alternative. In the mean time, you should not rely on any command using
standard input at all if you are using the parallel execution feature; but
if you are not using this feature, then standard input works normally in
all commands.
If a command fails (is killed by a signal or exits with a nonzero
status), and errors are not ignored for that command
(see section Errors in Commands),
the remaining command lines to remake the same target will not be run.
If a command fails and the `-k' or `--keep-going'
option was not given
(see section Summary of Options),
make aborts execution. If make
terminates for any reason (including a signal) with child processes
running, it waits for them to finish before actually exiting.
When the system is heavily loaded, you will probably want to run fewer jobs
than when it is lightly loaded. You can use the `-l' option to tell
make to limit the number of jobs to run at once, based on the load
average. The `-l' or `--max-load'
option is followed by a floating-point number. For
example,
-l 2.5
will not let make start more than one job if the load average is
above 2.5. The `-l' option with no following number removes the
load limit, if one was given with a previous `-l' option.
More precisely, when make goes to start up a job, and it already has
at least one job running, it checks the current load average; if it is not
lower than the limit given with `-l', make waits until the load
average goes below that limit, or until all the other jobs finish.
After each shell command returns, make looks at its exit status.
If the command completed successfully, the next command line is executed
in a new shell; after the last command line is finished, the rule is
finished.
If there is an error (the exit status is nonzero), make gives up on
the current rule, and perhaps on all rules.
Sometimes the failure of a certain command does not indicate a problem.
For example, you may use the mkdir command to ensure that a
directory exists. If the directory already exists, mkdir will
report an error, but you probably want make to continue regardless.
To ignore errors in a command line, write a `-' at the beginning of
the line's text (after the initial tab). The `-' is discarded before
the command is passed to the shell for execution.
For example,
clean:
-rm -f *.o
This causes rm to continue even if it is unable to remove a file.
When you run make with the `-i' or `--ignore-errors'
flag, errors are ignored in all commands of all rules. A rule in the
makefile for the special target .IGNORE has the same effect, if
there are no prerequisites. These ways of ignoring errors are obsolete
because `-' is more flexible.
When errors are to be ignored, because of either a `-' or the
`-i' flag, make treats an error return just like success,
except that it prints out a message that tells you the status code
the command exited with, and says that the error has been ignored.
When an error happens that make has not been told to ignore,
it implies that the current target cannot be correctly remade, and neither
can any other that depends on it either directly or indirectly. No further
commands will be executed for these targets, since their preconditions
have not been achieved.
Normally make gives up immediately in this circumstance, returning a
nonzero status. However, if the `-k' or `--keep-going'
flag is specified, make
continues to consider the other prerequisites of the pending targets,
remaking them if necessary, before it gives up and returns nonzero status.
For example, after an error in compiling one object file, `make -k'
will continue compiling other object files even though it already knows
that linking them will be impossible. See section Summary of Options.
The usual behavior assumes that your purpose is to get the specified
targets up to date; once make learns that this is impossible, it
might as well report the failure immediately. The `-k' option says
that the real purpose is to test as many of the changes made in the
program as possible, perhaps to find several independent problems so
that you can correct them all before the next attempt to compile. This
is why Emacs' compile command passes the `-k' flag by
default.
Usually when a command fails, if it has changed the target file at all,
the file is corrupted and cannot be used--or at least it is not
completely updated. Yet the file's timestamp says that it is now up to
date, so the next time make runs, it will not try to update that
file. The situation is just the same as when the command is killed by a
signal; see section Interrupting or Killing make. So generally the right thing to do is to
delete the target file if the command fails after beginning to change
the file. make will do this if .DELETE_ON_ERROR appears
as a target. This is almost always what you want make to do, but
it is not historical practice; so for compatibility, you must explicitly
request it.
If make gets a fatal signal while a command is executing, it may
delete the target file that the command was supposed to update. This is
done if the target file's last-modification time has changed since
make first checked it.
The purpose of deleting the target is to make sure that it is remade from
scratch when make is next run. Why is this? Suppose you type
Ctrl-c while a compiler is running, and it has begun to write an
object file `foo.o'. The Ctrl-c kills the compiler, resulting
in an incomplete file whose last-modification time is newer than the source
file `foo.c'. But make also receives the Ctrl-c signal
and deletes this incomplete file. If make did not do this, the next
invocation of make would think that `foo.o' did not require
updating--resulting in a strange error message from the linker when it
tries to link an object file half of which is missing.
You can prevent the deletion of a target file in this way by making the
special target .PRECIOUS depend on it. Before remaking a target,
make checks to see whether it appears on the prerequisites of
.PRECIOUS, and thereby decides whether the target should be deleted
if a signal happens. Some reasons why you might do this are that the
target is updated in some atomic fashion, or exists only to record a
modification-time (its contents do not matter), or must exist at all
times to prevent other sorts of trouble.
Recursive use of make means using make as a command in a
makefile. This technique is useful when you want separate makefiles for
various subsystems that compose a larger system. For example, suppose you
have a subdirectory `subdir' which has its own makefile, and you would
like the containing directory's makefile to run make on the
subdirectory. You can do it by writing this:
You can write recursive make commands just by copying this example,
but there are many things to know about how they work and why, and about
how the sub-make relates to the top-level make.
For your convenience, GNU make sets the variable CURDIR to
the pathname of the current working directory for you. If -C is
in effect, it will contain the path of the new directory, not the
original. The value has the same precedence it would have if it were
set in the makefile (by default, an environment variable CURDIR
will not override this value). Note that setting this variable has no
effect on the operation of make
Recursive make commands should always use the variable MAKE,
not the explicit command name `make', as shown here:
subsystem:
cd subdir && $(MAKE)
The value of this variable is the file name with which make was
invoked. If this file name was `/bin/make', then the command executed
is `cd subdir && /bin/make'. If you use a special version of
make to run the top-level makefile, the same special version will be
executed for recursive invocations.
As a special feature, using the variable MAKE in the commands of
a rule alters the effects of the `-t' (`--touch'), `-n'
(`--just-print'), or `-q' (`--question') option.
Using the MAKE variable has the same effect as using a `+'
character at the beginning of the command line. See section Instead of Executing the Commands.
Consider the command `make -t' in the above example. (The
`-t' option marks targets as up to date without actually running
any commands; see section Instead of Executing the Commands.) Following the usual
definition of `-t', a `make -t' command in the example would
create a file named `subsystem' and do nothing else. What you
really want it to do is run `cd subdir && make -t'; but that would
require executing the command, and `-t' says not to execute
commands.
The special feature makes this do what you want: whenever a command
line of a rule contains the variable MAKE, the flags `-t',
`-n' and `-q' do not apply to that line. Command lines
containing MAKE are executed normally despite the presence of a
flag that causes most commands not to be run. The usual
MAKEFLAGS mechanism passes the flags to the sub-make
(see section Communicating Options to a Sub-make), so your request to touch the files, or print the
commands, is propagated to the subsystem.
Variable values of the top-level make can be passed to the
sub-make through the environment by explicit request. These
variables are defined in the sub-make as defaults, but do not
override what is specified in the makefile used by the sub-make
makefile unless you use the `-e' switch (see section Summary of Options).
To pass down, or export, a variable, make adds the variable
and its value to the environment for running each command. The
sub-make, in turn, uses the environment to initialize its table
of variable values. See section Variables from the Environment.
Except by explicit request, make exports a variable only if it
is either defined in the environment initially or set on the command
line, and if its name consists only of letters, numbers, and underscores.
Some shells cannot cope with environment variable names consisting of
characters other than letters, numbers, and underscores.
The special variables SHELL and MAKEFLAGS are always
exported (unless you unexport them).
MAKEFILES is exported if you set it to anything.
make automatically passes down variable values that were defined
on the command line, by putting them in the MAKEFLAGS variable.
See the next section.
Variables are not normally passed down if they were created by
default by make (see section Variables Used by Implicit Rules). The sub-make will define these for
itself.
If you want to export specific variables to a sub-make, use the
export directive, like this:
export variable ...
If you want to prevent a variable from being exported, use the
unexport directive, like this:
unexport variable ...
As a convenience, you can define a variable and export it at the same
time by doing:
You may notice that the export and unexport directives
work in make in the same way they work in the shell, sh.
If you want all variables to be exported by default, you can use
export by itself:
export
This tells make that variables which are not explicitly mentioned
in an export or unexport directive should be exported.
Any variable given in an unexport directive will still not
be exported. If you use export by itself to export variables by
default, variables whose names contain characters other than
alphanumerics and underscores will not be exported unless specifically
mentioned in an export directive.
The behavior elicited by an export directive by itself was the
default in older versions of GNU make. If your makefiles depend
on this behavior and you want to be compatible with old versions of
make, you can write a rule for the special target
.EXPORT_ALL_VARIABLES instead of using the export directive.
This will be ignored by old makes, while the export
directive will cause a syntax error.
Likewise, you can use unexport by itself to tell makenot to export variables by default. Since this is the default
behavior, you would only need to do this if export had been used
by itself earlier (in an included makefile, perhaps). You
cannot use export and unexport by themselves to
have variables exported for some commands and not for others. The last
export or unexport directive that appears by itself
determines the behavior for the entire run of make.
As a special feature, the variable MAKELEVEL is changed when it
is passed down from level to level. This variable's value is a string
which is the depth of the level as a decimal number. The value is
`0' for the top-level make; `1' for a sub-make,
`2' for a sub-sub-make, and so on. The incrementation
happens when make sets up the environment for a command.
The main use of MAKELEVEL is to test it in a conditional
directive (see section Conditional Parts of Makefiles); this
way you can write a makefile that behaves one way if run recursively and
another way if run directly by you.
You can use the variable MAKEFILES to cause all sub-make
commands to use additional makefiles. The value of MAKEFILES is
a whitespace-separated list of file names. This variable, if defined in
the outer-level makefile, is passed down through the environment; then
it serves as a list of extra makefiles for the sub-make to read
before the usual or specified ones. See section The Variable MAKEFILES.
Flags such as `-s' and `-k' are passed automatically to the
sub-make through the variable MAKEFLAGS. This variable is
set up automatically by make to contain the flag letters that
make received. Thus, if you do `make -ks' then
MAKEFLAGS gets the value `ks'.
As a consequence, every sub-make gets a value for MAKEFLAGS
in its environment. In response, it takes the flags from that value and
processes them as if they had been given as arguments.
See section Summary of Options.
Likewise variables defined on the command line are passed to the
sub-make through MAKEFLAGS. Words in the value of
MAKEFLAGS that contain `=', make treats as variable
definitions just as if they appeared on the command line.
See section Overriding Variables.
The options `-C', `-f', `-o', and `-W' are not put
into MAKEFLAGS; these options are not passed down.
The `-j' option is a special case (see section Parallel Execution).
If you set it to some numeric value `N' and your operating system
supports it (most any UNIX system will; others typically won't), the
parent make and all the sub-makes will communicate to
ensure that there are only `N' jobs running at the same time
between them all. Note that any job that is marked recursive
(see section Instead of Executing the Commands)
doesn't count against the total jobs (otherwise we could get `N'
sub-makes running and have no slots left over for any real work!)
If your operating system doesn't support the above communication, then
`-j 1' is always put into MAKEFLAGS instead of the value you
specified. This is because if the `-j' option were passed down
to sub-makes, you would get many more jobs running in parallel
than you asked for. If you give `-j' with no numeric argument,
meaning to run as many jobs as possible in parallel, this is passed
down, since multiple infinities are no more than one.
If you do not want to pass the other flags down, you must change the
value of MAKEFLAGS, like this:
subsystem:
cd subdir && $(MAKE) MAKEFLAGS=
The command line variable definitions really appear in the variable
MAKEOVERRIDES, and MAKEFLAGS contains a reference to this
variable. If you do want to pass flags down normally, but don't want to
pass down the command line variable definitions, you can reset
MAKEOVERRIDES to empty, like this:
MAKEOVERRIDES =
This is not usually useful to do. However, some systems have a small
fixed limit on the size of the environment, and putting so much
information into the value of MAKEFLAGS can exceed it. If you
see the error message `Arg list too long', this may be the problem.
(For strict compliance with POSIX.2, changing MAKEOVERRIDES does
not affect MAKEFLAGS if the special target `.POSIX' appears
in the makefile. You probably do not care about this.)
A similar variable MFLAGS exists also, for historical
compatibility. It has the same value as MAKEFLAGS except that it
does not contain the command line variable definitions, and it always
begins with a hyphen unless it is empty (MAKEFLAGS begins with a
hyphen only when it begins with an option that has no single-letter
version, such as `--warn-undefined-variables'). MFLAGS was
traditionally used explicitly in the recursive make command, like
this:
subsystem:
cd subdir && $(MAKE) $(MFLAGS)
but now MAKEFLAGS makes this usage redundant. If you want your
makefiles to be compatible with old make programs, use this
technique; it will work fine with more modern make versions too.
The MAKEFLAGS variable can also be useful if you want to have
certain options, such as `-k' (see section Summary of Options), set each time you run make. You simply put a value for
MAKEFLAGS in your environment. You can also set MAKEFLAGS in
a makefile, to specify additional flags that should also be in effect for
that makefile. (Note that you cannot use MFLAGS this way. That
variable is set only for compatibility; make does not interpret a
value you set for it in any way.)
When make interprets the value of MAKEFLAGS (either from the
environment or from a makefile), it first prepends a hyphen if the value
does not already begin with one. Then it chops the value into words
separated by blanks, and parses these words as if they were options given
on the command line (except that `-C', `-f', `-h',
`-o', `-W', and their long-named versions are ignored; and there
is no error for an invalid option).
If you do put MAKEFLAGS in your environment, you should be sure not
to include any options that will drastically affect the actions of
make and undermine the purpose of makefiles and of make
itself. For instance, the `-t', `-n', and `-q' options, if
put in one of these variables, could have disastrous consequences and would
certainly have at least surprising and probably annoying effects.
If you use several levels of recursive make invocations, the
`-w' or `--print-directory' option can make the output a
lot easier to understand by showing each directory as make
starts processing it and as make finishes processing it. For
example, if `make -w' is run in the directory `/u/gnu/make',
make will print a line of the form:
make: Entering directory `/u/gnu/make'.
before doing anything else, and a line of the form:
make: Leaving directory `/u/gnu/make'.
when processing is completed.
Normally, you do not need to specify this option because `make'
does it for you: `-w' is turned on automatically when you use the
`-C' option, and in sub-makes. make will not
automatically turn on `-w' if you also use `-s', which says to
be silent, or if you use `--no-print-directory' to explicitly
disable it.
When the same sequence of commands is useful in making various targets, you
can define it as a canned sequence with the define directive, and
refer to the canned sequence from the rules for those targets. The canned
sequence is actually a variable, so the name must not conflict with other
variable names.
Here is an example of defining a canned sequence of commands:
Here run-yacc is the name of the variable being defined;
endef marks the end of the definition; the lines in between are the
commands. The define directive does not expand variable references
and function calls in the canned sequence; the `$' characters,
parentheses, variable names, and so on, all become part of the value of the
variable you are defining.
See section Defining Variables Verbatim,
for a complete explanation of define.
The first command in this example runs Yacc on the first prerequisite of
whichever rule uses the canned sequence. The output file from Yacc is
always named `y.tab.c'. The second command moves the output to the
rule's target file name.
To use the canned sequence, substitute the variable into the commands of a
rule. You can substitute it like any other variable
(see section Basics of Variable References).
Because variables defined by define are recursively expanded
variables, all the variable references you wrote inside the define
are expanded now. For example:
foo.c : foo.y
$(run-yacc)
`foo.y' will be substituted for the variable `$^' when it occurs in
run-yacc's value, and `foo.c' for `$@'.
This is a realistic example, but this particular one is not needed in
practice because make has an implicit rule to figure out these
commands based on the file names involved
(see section Using Implicit Rules).
In command execution, each line of a canned sequence is treated just as
if the line appeared on its own in the rule, preceded by a tab. In
particular, make invokes a separate subshell for each line. You
can use the special prefix characters that affect command lines
(`@', `-', and `+') on each line of a canned sequence.
See section Writing the Commands in Rules.
For example, using this canned sequence:
It is sometimes useful to define commands which do nothing. This is done
simply by giving a command that consists of nothing but whitespace. For
example:
target: ;
defines an empty command string for `target'. You could also use a
line beginning with a tab character to define an empty command string,
but this would be confusing because such a line looks empty.
You may be wondering why you would want to define a command string that
does nothing. The only reason this is useful is to prevent a target
from getting implicit commands (from implicit rules or the
.DEFAULT special target; see section Using Implicit Rules and
see section Defining Last-Resort Default Rules).
You may be inclined to define empty command strings for targets that are
not actual files, but only exist so that their prerequisites can be
remade. However, this is not the best way to do that, because the
prerequisites may not be remade properly if the target file actually does exist.
See section Phony Targets, for a better way to do this.
A variable is a name defined in a makefile to represent a string
of text, called the variable's value. These values are
substituted by explicit request into targets, prerequisites, commands,
and other parts of the makefile. (In some other versions of make,
variables are called macros.)
Variables and functions in all parts of a makefile are expanded when
read, except for the shell commands in rules, the right-hand sides of
variable definitions using `=', and the bodies of variable
definitions using the define directive.
Variables can represent lists of file names, options to pass to compilers,
programs to run, directories to look in for source files, directories to
write output in, or anything else you can imagine.
A variable name may be any sequence of characters not containing `:',
`#', `=', or leading or trailing whitespace. However,
variable names containing characters other than letters, numbers, and
underscores should be avoided, as they may be given special meanings in the
future, and with some shells they cannot be passed through the environment to a
sub-make
(see section Communicating Variables to a Sub-make).
Variable names are case-sensitive. The names `foo', `FOO',
and `Foo' all refer to different variables.
It is traditional to use upper case letters in variable names, but we
recommend using lower case letters for variable names that serve internal
purposes in the makefile, and reserving upper case for parameters that
control implicit rules or for parameters that the user should override with
command options (see section Overriding Variables).
A few variables have names that are a single punctuation character or
just a few characters. These are the automatic variables, and
they have particular specialized uses. See section Automatic Variables.
To substitute a variable's value, write a dollar sign followed by the name
of the variable in parentheses or braces: either `$(foo)' or
`${foo}' is a valid reference to the variable foo. This
special significance of `$' is why you must write `$$' to have
the effect of a single dollar sign in a file name or command.
Variable references can be used in any context: targets, prerequisites,
commands, most directives, and new variable values. Here is an
example of a common case, where a variable holds the names of all the
object files in a program:
objects = program.o foo.o utils.o
program : $(objects)
cc -o program $(objects)
$(objects) : defs.h
Variable references work by strict textual substitution. Thus, the rule
foo = c
prog.o : prog.$(foo)
$(foo)$(foo) -$(foo) prog.$(foo)
could be used to compile a C program `prog.c'. Since spaces before
the variable value are ignored in variable assignments, the value of
foo is precisely `c'. (Don't actually write your makefiles
this way!)
A dollar sign followed by a character other than a dollar sign,
open-parenthesis or open-brace treats that single character as the
variable name. Thus, you could reference the variable x with
`$x'. However, this practice is strongly discouraged, except in
the case of the automatic variables (see section Automatic Variables).
There are two ways that a variable in GNU make can have a value;
we call them the two flavors of variables. The two flavors are
distinguished in how they are defined and in what they do when expanded.
The first flavor of variable is a recursively expanded variable.
Variables of this sort are defined by lines using `='
(see section Setting Variables) or by the define directive
(see section Defining Variables Verbatim). The value you specify
is installed verbatim; if it contains references to other variables,
these references are expanded whenever this variable is substituted (in
the course of expanding some other string). When this happens, it is
called recursive expansion.
will echo `Huh?': `$(foo)' expands to `$(bar)' which
expands to `$(ugh)' which finally expands to `Huh?'.
This flavor of variable is the only sort supported by other versions of
make. It has its advantages and its disadvantages. An advantage
(most would say) is that:
will do what was intended: when `CFLAGS' is expanded in a command,
it will expand to `-Ifoo -Ibar -O'. A major disadvantage is that you
cannot append something on the end of a variable, as in
CFLAGS = $(CFLAGS) -O
because it will cause an infinite loop in the variable expansion.
(Actually make detects the infinite loop and reports an error.)
Another disadvantage is that any functions
(see section Functions for Transforming Text)
referenced in the definition will be executed every time the variable is
expanded. This makes make run slower; worse, it causes the
wildcard and shell functions to give unpredictable results
because you cannot easily control when they are called, or even how many
times.
To avoid all the problems and inconveniences of recursively expanded
variables, there is another flavor: simply expanded variables.
Simply expanded variables are defined by lines using `:='
(see section Setting Variables).
The value of a simply expanded variable is scanned
once and for all, expanding any references to other variables and
functions, when the variable is defined. The actual value of the simply
expanded variable is the result of expanding the text that you write.
It does not contain any references to other variables; it contains their
values as of the time this variable was defined. Therefore,
x := foo
y := $(x) bar
x := later
is equivalent to
y := foo bar
x := later
When a simply expanded variable is referenced, its value is substituted
verbatim.
Here is a somewhat more complicated example, illustrating the use of
`:=' in conjunction with the shell function.
(See section The shell Function.) This example
also shows use of the variable MAKELEVEL, which is changed
when it is passed down from level to level.
(See section Communicating Variables to a Sub-make, for information about MAKELEVEL.)
An advantage of this use of `:=' is that a typical
`descend into a directory' command then looks like this:
${subdirs}:
${MAKE} cur-dir=${cur-dir}/$@ -C $@ all
Simply expanded variables generally make complicated makefile programming
more predictable because they work like variables in most programming
languages. They allow you to redefine a variable using its own value (or
its value processed in some way by one of the expansion functions) and to
use the expansion functions much more efficiently
(see section Functions for Transforming Text).
You can also use them to introduce controlled leading whitespace into
variable values. Leading whitespace characters are discarded from your
input before substitution of variable references and function calls;
this means you can include leading spaces in a variable value by
protecting them with variable references, like this:
nullstring :=
space := $(nullstring) # end of the line
Here the value of the variable space is precisely one space. The
comment `# end of the line' is included here just for clarity.
Since trailing space characters are not stripped from variable
values, just a space at the end of the line would have the same effect
(but be rather hard to read). If you put whitespace at the end of a
variable value, it is a good idea to put a comment like that at the end
of the line to make your intent clear. Conversely, if you do not
want any whitespace characters at the end of your variable value, you
must remember not to put a random comment on the end of the line after
some whitespace, such as this:
dir := /foo/bar # directory to put the frobs in
Here the value of the variable dir is `/foo/bar '
(with four trailing spaces), which was probably not the intention.
(Imagine something like `$(dir)/file' with this definition!)
There is another assignment operator for variables, `?='. This
is called a conditional variable assignment operator, because it only
has an effect if the variable is not yet defined. This statement:
A substitution reference substitutes the value of a variable with
alterations that you specify. It has the form
`$(var:a=b)' (or
`${var:a=b}') and its meaning is to take the value
of the variable var, replace every a at the end of a word with
b in that value, and substitute the resulting string.
When we say "at the end of a word", we mean that a must appear
either followed by whitespace or at the end of the value in order to be
replaced; other occurrences of a in the value are unaltered. For
example:
A substitution reference is actually an abbreviation for use of the
patsubst expansion function (see section Functions for String Substitution and Analysis). We provide
substitution references as well as patsubst for compatibility with
other implementations of make.
Another type of substitution reference lets you use the full power of
the patsubst function. It has the same form
`$(var:a=b)' described above, except that now
a must contain a single `%' character. This case is
equivalent to `$(patsubst a,b,$(var))'.
See section Functions for String Substitution and Analysis,
for a description of the patsubst function.
For example:
foo := a.o b.o c.o
bar := $(foo:%.o=%.c)
Computed variable names are a complicated concept needed only for
sophisticated makefile programming. For most purposes you need not
consider them, except to know that making a variable with a dollar sign
in its name might have strange results. However, if you are the type
that wants to understand everything, or you are actually interested in
what they do, read on.
Variables may be referenced inside the name of a variable. This is
called a computed variable name or a nested variable
reference. For example,
x = y
y = z
a := $($(x))
defines a as `z': the `$(x)' inside `$($(x))' expands
to `y', so `$($(x))' expands to `$(y)' which in turn expands
to `z'. Here the name of the variable to reference is not stated
explicitly; it is computed by expansion of `$(x)'. The reference
`$(x)' here is nested within the outer variable reference.
The previous example shows two levels of nesting, but any number of levels
is possible. For example, here are three levels:
x = y
y = z
z = u
a := $($($(x)))
Here the innermost `$(x)' expands to `y', so `$($(x))'
expands to `$(y)' which in turn expands to `z'; now we have
`$(z)', which becomes `u'.
References to recursively-expanded variables within a variable name are
reexpanded in the usual fashion. For example:
x = $(y)
y = z
z = Hello
a := $($(x))
defines a as `Hello': `$($(x))' becomes `$($(y))'
which becomes `$(z)' which becomes `Hello'.
x = variable1
variable2 := Hello
y = $(subst 1,2,$(x))
z = y
a := $($($(z)))
eventually defines a as `Hello'. It is doubtful that anyone
would ever want to write a nested reference as convoluted as this one, but
it works: `$($($(z)))' expands to `$($(y))' which becomes
`$($(subst 1,2,$(x)))'. This gets the value `variable1' from
x and changes it by substitution to `variable2', so that the
entire string becomes `$(variable2)', a simple variable reference
whose value is `Hello'.
A computed variable name need not consist entirely of a single variable
reference. It can contain several variable references, as well as some
invariant text. For example,
defines sources as either `a.c b.c c.c' or `1.c 2.c 3.c',
depending on the value of a1.
The only restriction on this sort of use of nested variable references
is that they cannot specify part of the name of a function to be called.
This is because the test for a recognized function name is done before
the expansion of nested references. For example,
ifdef do_sort
func := sort
else
func := strip
endif
bar := a d b g q c
foo := $($(func) $(bar))
attempts to give `foo' the value of the variable `sort a d b g
q c' or `strip a d b g q c', rather than giving `a d b g q c'
as the argument to either the sort or the strip function.
This restriction could be removed in the future if that change is shown
to be a good idea.
You can also use computed variable names in the left-hand side of a
variable assignment, or in a define directive, as in:
This example defines the variables `dir', `foo_sources', and
`foo_print'.
Note that nested variable references are quite different from
recursively expanded variables
(see section The Two Flavors of Variables), though both are
used together in complex ways when doing makefile programming.
To set a variable from the makefile, write a line starting with the
variable name followed by `=' or `:='. Whatever follows the
`=' or `:=' on the line becomes the value. For example,
objects = main.o foo.o bar.o utils.o
defines a variable named objects. Whitespace around the variable
name and immediately after the `=' is ignored.
Variables defined with `=' are recursively expanded variables.
Variables defined with `:=' are simply expanded variables; these
definitions can contain variable references which will be expanded before
the definition is made. See section The Two Flavors of Variables.
The variable name may contain function and variable references, which
are expanded when the line is read to find the actual variable name to use.
There is no limit on the length of the value of a variable except the
amount of swapping space on the computer. When a variable definition is
long, it is a good idea to break it into several lines by inserting
backslash-newline at convenient places in the definition. This will not
affect the functioning of make, but it will make the makefile easier
to read.
Most variable names are considered to have the empty string as a value if
you have never set them. Several variables have built-in initial values
that are not empty, but you can set them in the usual ways
(see section Variables Used by Implicit Rules).
Several special variables are set
automatically to a new value for each rule; these are called the
automatic variables (see section Automatic Variables).
If you'd like a variable to be set to a value only if it's not already
set, then you can use the shorthand operator `?=' instead of
`='. These two settings of the variable `FOO' are identical
(see section The origin Function):
but differs in ways that become important when you use more complex values.
When the variable in question has not been defined before, `+='
acts just like normal `=': it defines a recursively-expanded
variable. However, when there is a previous definition, exactly
what `+=' does depends on what flavor of variable you defined
originally. See section The Two Flavors of Variables, for an
explanation of the two flavors of variables.
When you add to a variable's value with `+=', make acts
essentially as if you had included the extra text in the initial
definition of the variable. If you defined it first with `:=',
making it a simply-expanded variable, `+=' adds to that
simply-expanded definition, and expands the new text before appending it
to the old value just as `:=' does
(see section Setting Variables, for a full explanation of `:=').
In fact,
variable := value
variable += more
is exactly equivalent to:
variable := value
variable := $(variable) more
On the other hand, when you use `+=' with a variable that you defined
first to be recursively-expanded using plain `=', make does
something a bit different. Recall that when you define a
recursively-expanded variable, make does not expand the value you set
for variable and function references immediately. Instead it stores the text
verbatim, and saves these variable and function references to be expanded
later, when you refer to the new variable (see section The Two Flavors of Variables). When you use `+=' on a recursively-expanded variable,
it is this unexpanded text to which make appends the new text you
specify.
variable = value
variable += more
is roughly equivalent to:
temp = value
variable = $(temp) more
except that of course it never defines a variable called temp.
The importance of this comes when the variable's old value contains
variable references. Take this common example:
The first line defines the CFLAGS variable with a reference to another
variable, includes. (CFLAGS is used by the rules for C
compilation; see section Catalogue of Implicit Rules.)
Using `=' for the definition makes CFLAGS a recursively-expanded
variable, meaning `$(includes) -O' is not expanded when
make processes the definition of CFLAGS. Thus, includes
need not be defined yet for its value to take effect. It only has to be
defined before any reference to CFLAGS. If we tried to append to the
value of CFLAGS without using `+=', we might do it like this:
CFLAGS := $(CFLAGS) -pg # enable profiling
This is pretty close, but not quite what we want. Using `:='
redefines CFLAGS as a simply-expanded variable; this means
make expands the text `$(CFLAGS) -pg' before setting the
variable. If includes is not yet defined, we get ` -O
-pg', and a later definition of includes will have no effect.
Conversely, by using `+=' we set CFLAGS to the
unexpanded value `$(includes) -O -pg'. Thus we preserve
the reference to includes, so if that variable gets defined at
any later point, a reference like `$(CFLAGS)' still uses its
value.
If a variable has been set with a command argument
(see section Overriding Variables),
then ordinary assignments in the makefile are ignored. If you want to set
the variable in the makefile even though it was set with a command
argument, you can use an override directive, which is a line that
looks like this:
override variable = value
or
override variable := value
To append more text to a variable defined on the command line, use:
The override directive was not invented for escalation in the war
between makefiles and command arguments. It was invented so you can alter
and add to values that the user specifies with command arguments.
For example, suppose you always want the `-g' switch when you run the
C compiler, but you would like to allow the user to specify the other
switches with a command argument just as usual. You could use this
override directive:
override CFLAGS += -g
You can also use override directives with define directives.
This is done as you might expect:
override define foo
bar
endef
See the next section for information about define.
Another way to set the value of a variable is to use the define
directive. This directive has an unusual syntax which allows newline
characters to be included in the value, which is convenient for defining
canned sequences of commands
(see section Defining Canned Command Sequences).
The define directive is followed on the same line by the name of the
variable and nothing more. The value to give the variable appears on the
following lines. The end of the value is marked by a line containing just
the word endef. Aside from this difference in syntax, define
works just like `=': it creates a recursively-expanded variable
(see section The Two Flavors of Variables).
The variable name may contain function and variable references, which
are expanded when the directive is read to find the actual variable name
to use.
define two-lines
echo foo
echo $(bar)
endef
The value in an ordinary assignment cannot contain a newline; but the
newlines that separate the lines of the value in a define become
part of the variable's value (except for the final newline which precedes
the endef and is not considered part of the value).
The previous example is functionally equivalent to this:
two-lines = echo foo; echo $(bar)
since two commands separated by semicolon behave much like two separate
shell commands. However, note that using two separate lines means
make will invoke the shell twice, running an independent subshell
for each line. See section Command Execution.
If you want variable definitions made with define to take
precedence over command-line variable definitions, you can use the
override directive together with define:
Variables in make can come from the environment in which
make is run. Every environment variable that make sees when
it starts up is transformed into a make variable with the same name
and value. But an explicit assignment in the makefile, or with a command
argument, overrides the environment. (If the `-e' flag is specified,
then values from the environment override assignments in the makefile.
See section Summary of Options.
But this is not recommended practice.)
Thus, by setting the variable CFLAGS in your environment, you can
cause all C compilations in most makefiles to use the compiler switches you
prefer. This is safe for variables with standard or conventional meanings
because you know that no makefile will use them for other things. (But
this is not totally reliable; some makefiles set CFLAGS explicitly
and therefore are not affected by the value in the environment.)
When make is invoked recursively, variables defined in the
outer invocation can be passed to inner invocations through the
environment (see section Recursive Use of make). By
default, only variables that came from the environment or the command
line are passed to recursive invocations. You can use the
export directive to pass other variables.
See section Communicating Variables to a Sub-make, for full details.
Other use of variables from the environment is not recommended. It is not
wise for makefiles to depend for their functioning on environment variables
set up outside their control, since this would cause different users to get
different results from the same makefile. This is against the whole
purpose of most makefiles.
Such problems would be especially likely with the variable SHELL,
which is normally present in the environment to specify the user's choice
of interactive shell. It would be very undesirable for this choice to
affect make. So make ignores the environment value of
SHELL (except on MS-DOS and MS-Windows, where SHELL is
usually not set. See section Command Execution.)
Variable values in make are usually global; that is, they are the
same regardless of where they are evaluated (unless they're reset, of
course). One exception to that is automatic variables
(see section Automatic Variables).
The other exception is target-specific variable values. This
feature allows you to define different values for the same variable,
based on the target that make is currently building. As with
automatic variables, these values are only available within the context
of a target's command script (and in other target-specific assignments).
Set a target-specific variable value like this:
target ... : variable-assignment
or like this:
target ... : override variable-assignment
Multiple target values create a target-specific variable value for
each member of the target list individually.
The variable-assignment can be any valid form of assignment;
recursive (`='), static (`:='), appending (`+='), or
conditional (`?='). All variables that appear within the
variable-assignment are evaluated within the context of the
target: thus, any previously-defined target-specific variable values
will be in effect. Note that this variable is actually distinct from
any "global" value: the two variables do not have to have the same
flavor (recursive vs. static).
Target-specific variables have the same priority as any other makefile
variable. Variables provided on the command-line (and in the
environment if the `-e' option is in force) will take precedence.
Specifying the override directive will allow the target-specific
variable value to be preferred.
There is one more special feature of target-specific variables: when you
define a target-specific variable, that variable value is also in effect
for all prerequisites of this target (unless those prerequisites override
it with their own target-specific variable value). So, for example, a
statement like this:
prog : CFLAGS = -g
prog : prog.o foo.o bar.o
will set CFLAGS to `-g' in the command script for
`prog', but it will also set CFLAGS to `-g' in the
command scripts that create `prog.o', `foo.o', and
`bar.o', and any command scripts which create their prerequisites.
In addition to target-specific variable values (see section Target-specific Variable Values), GNU make supports
pattern-specific variable values. In this form, a variable is defined
for any target that matches the pattern specified. Variables defined in
this way are searched after any target-specific variables defined
explicitly for that target, and before target-specific variables defined
for the parent target.
Set a pattern-specific variable value like this:
pattern ... : variable-assignment
or like this:
pattern ... : override variable-assignment
where pattern is a %-pattern. As with target-specific variable
values, multiple pattern values create a pattern-specific variable
value for each pattern individually. The variable-assignment can
be any valid form of assignment. Any command-line variable setting will
take precedence, unless override is specified.
For example:
%.o : CFLAGS = -O
will assign CFLAGS the value of `-O' for all targets
matching the pattern %.o.
A conditional causes part of a makefile to be obeyed or ignored
depending on the values of variables. Conditionals can compare the
value of one variable to another, or the value of a variable to
a constant string. Conditionals control what make actually
"sees" in the makefile, so they cannot be used to control shell
commands at the time of execution.
The following example of a conditional tells make to use one set
of libraries if the CC variable is `gcc', and a different
set of libraries otherwise. It works by controlling which of two
command lines will be used as the command for a rule. The result is
that `CC=gcc' as an argument to make changes not only which
compiler is used but also which libraries are linked.
This conditional uses three directives: one ifeq, one else
and one endif.
The ifeq directive begins the conditional, and specifies the
condition. It contains two arguments, separated by a comma and surrounded
by parentheses. Variable substitution is performed on both arguments and
then they are compared. The lines of the makefile following the
ifeq are obeyed if the two arguments match; otherwise they are
ignored.
The else directive causes the following lines to be obeyed if the
previous conditional failed. In the example above, this means that the
second alternative linking command is used whenever the first alternative
is not used. It is optional to have an else in a conditional.
The endif directive ends the conditional. Every conditional must
end with an endif. Unconditional makefile text follows.
As this example illustrates, conditionals work at the textual level:
the lines of the conditional are treated as part of the makefile, or
ignored, according to the condition. This is why the larger syntactic
units of the makefile, such as rules, may cross the beginning or the
end of the conditional.
When the variable CC has the value `gcc', the above example has
this effect:
The syntax of a simple conditional with no else is as follows:
conditional-directivetext-if-true
endif
The text-if-true may be any lines of text, to be considered as part
of the makefile if the condition is true. If the condition is false, no
text is used instead.
The syntax of a complex conditional is as follows:
If the condition is true, text-if-true is used; otherwise,
text-if-false is used instead. The text-if-false can be any
number of lines of text.
The syntax of the conditional-directive is the same whether the
conditional is simple or complex. There are four different directives that
test different conditions. Here is a table of them:
ifeq (arg1, arg2)
ifeq 'arg1' 'arg2'
ifeq "arg1" "arg2"
ifeq "arg1" 'arg2'
ifeq 'arg1' "arg2"
Expand all variable references in arg1 and arg2 and
compare them. If they are identical, the text-if-true is
effective; otherwise, the text-if-false, if any, is effective.
Often you want to test if a variable has a non-empty value. When the
value results from complex expansions of variables and functions,
expansions you would consider empty may actually contain whitespace
characters and thus are not seen as empty. However, you can use the
strip function (see section Functions for String Substitution and Analysis) to avoid interpreting
whitespace as a non-empty value. For example:
ifeq ($(strip $(foo)),)
text-if-empty
endif
will evaluate text-if-empty even if the expansion of
$(foo) contains whitespace characters.
ifneq (arg1, arg2)
ifneq 'arg1' 'arg2'
ifneq "arg1" "arg2"
ifneq "arg1" 'arg2'
ifneq 'arg1' "arg2"
Expand all variable references in arg1 and arg2 and
compare them. If they are different, the text-if-true is
effective; otherwise, the text-if-false, if any, is effective.
ifdef variable-name
If the variable variable-name has a non-empty value, the
text-if-true is effective; otherwise, the text-if-false,
if any, is effective. Variables that have never been defined have an
empty value.
Note that ifdef only tests whether a variable has a value. It
does not expand the variable to see if that value is nonempty.
Consequently, tests using ifdef return true for all definitions
except those like foo =. To test for an empty value, use
ifeq ($(foo),). For example,
bar =
foo = $(bar)
ifdef foo
frobozz = yes
else
frobozz = no
endif
If the variable variable-name has an empty value, the
text-if-true is effective; otherwise, the text-if-false,
if any, is effective.
Extra spaces are allowed and ignored at the beginning of the conditional
directive line, but a tab is not allowed. (If the line begins with a tab,
it will be considered a command for a rule.) Aside from this, extra spaces
or tabs may be inserted with no effect anywhere except within the directive
name or within an argument. A comment starting with `#' may appear at
the end of the line.
The other two directives that play a part in a conditional are else
and endif. Each of these directives is written as one word, with no
arguments. Extra spaces are allowed and ignored at the beginning of the
line, and spaces or tabs at the end. A comment starting with `#' may
appear at the end of the line.
Conditionals affect which lines of the makefile make uses. If
the condition is true, make reads the lines of the
text-if-true as part of the makefile; if the condition is false,
make ignores those lines completely. It follows that syntactic
units of the makefile, such as rules, may safely be split across the
beginning or the end of the conditional.
make evaluates conditionals when it reads a makefile.
Consequently, you cannot use automatic variables in the tests of
conditionals because they are not defined until commands are run
(see section Automatic Variables).
To prevent intolerable confusion, it is not permitted to start a
conditional in one makefile and end it in another. However, you may
write an include directive within a conditional, provided you do
not attempt to terminate the conditional inside the included file.
You can write a conditional that tests make command flags such as
`-t' by using the variable MAKEFLAGS together with the
findstring function
(see section Functions for String Substitution and Analysis).
This is useful when touch is not enough to make a file appear up
to date.
The findstring function determines whether one string appears as a
substring of another. If you want to test for the `-t' flag,
use `t' as the first string and the value of MAKEFLAGS as
the other.
For example, here is how to arrange to use `ranlib -t' to finish
marking an archive file up to date:
Functions allow you to do text processing in the makefile to compute
the files to operate on or the commands to use. You use a function in a
function call, where you give the name of the function and some text
(the arguments) for the function to operate on. The result of the
function's processing is substituted into the makefile at the point of the
call, just as a variable might be substituted.
A function call resembles a variable reference. It looks like this:
$(functionarguments)
or like this:
${functionarguments}
Here function is a function name; one of a short list of names
that are part of make. You can also essentially create your own
functions by using the call builtin function.
The arguments are the arguments of the function. They are
separated from the function name by one or more spaces or tabs, and if
there is more than one argument, then they are separated by commas.
Such whitespace and commas are not part of an argument's value. The
delimiters which you use to surround the function call, whether
parentheses or braces, can appear in an argument only in matching pairs;
the other kind of delimiters may appear singly. If the arguments
themselves contain other function calls or variable references, it is
wisest to use the same kind of delimiters for all the references; write
`$(subst a,b,$(x))', not `$(subst a,b,${x})'. This
is because it is clearer, and because only one type of delimiter is
matched to find the end of the reference.
The text written for each argument is processed by substitution of
variables and function calls to produce the argument value, which
is the text on which the function acts. The substitution is done in the
order in which the arguments appear.
Commas and unmatched parentheses or braces cannot appear in the text of an
argument as written; leading spaces cannot appear in the text of the first
argument as written. These characters can be put into the argument value
by variable substitution. First define variables comma and
space whose values are isolated comma and space characters, then
substitute these variables where such characters are wanted, like this:
comma:= ,
empty:=
space:= $(empty) $(empty)
foo:= a b c
bar:= $(subst $(space),$(comma),$(foo))
# bar is now `a,b,c'.
Here the subst function replaces each space with a comma, through
the value of foo, and substitutes the result.
Performs a textual replacement on the text text: each occurrence
of from is replaced by to. The result is substituted for
the function call. For example,
$(subst ee,EE,feet on the street)
substitutes the string `fEEt on the strEEt'.
$(patsubst pattern,replacement,text)
Finds whitespace-separated words in text that match
pattern and replaces them with replacement. Here
pattern may contain a `%' which acts as a wildcard,
matching any number of any characters within a word. If
replacement also contains a `%', the `%' is replaced
by the text that matched the `%' in pattern.
`%' characters in patsubst function invocations can be
quoted with preceding backslashes (`\'). Backslashes that would
otherwise quote `%' characters can be quoted with more backslashes.
Backslashes that quote `%' characters or other backslashes are
removed from the pattern before it is compared file names or has a stem
substituted into it. Backslashes that are not in danger of quoting
`%' characters go unmolested. For example, the pattern
`the\%weird\\%pattern\\' has `the%weird\' preceding the
operative `%' character, and `pattern\\' following it. The
final two backslashes are left alone because they cannot affect any
`%' character.
Whitespace between words is folded into single space characters;
leading and trailing whitespace is discarded.
For example,
$(patsubst %.c,%.o,x.c.c bar.c)
produces the value `x.c.o bar.o'.
Substitution references (see section Substitution References) are a simpler way to get the effect of the patsubst
function:
$(var:pattern=replacement)
is equivalent to
$(patsubst pattern,replacement,$(var))
The second shorthand simplifies one of the most common uses of
patsubst: replacing the suffix at the end of file names.
$(var:suffix=replacement)
is equivalent to
$(patsubst %suffix,%replacement,$(var))
For example, you might have a list of object files:
objects = foo.o bar.o baz.o
To get the list of corresponding source files, you could simply write:
$(objects:.o=.c)
instead of using the general form:
$(patsubst %.o,%.c,$(objects))
$(strip string)
Removes leading and trailing whitespace from string and replaces
each internal sequence of one or more whitespace characters with a
single space. Thus, `$(strip a b c )' results in `a b c'.
The function strip can be very useful when used in conjunction
with conditionals. When comparing something with the empty string
`' using ifeq or ifneq, you usually want a string of
just whitespace to match the empty string (see section Conditional Parts of Makefiles).
Thus, the following may fail to have the desired results:
.PHONY: all
ifneq "$(needs_made)" ""
all: $(needs_made)
else
all:;@echo 'Nothing to make!'
endif
Replacing the variable reference `$(needs_made)' with the
function call `$(strip $(needs_made))' in the ifneq
directive would make it more robust.
$(findstring find,in)
Searches in for an occurrence of find. If it occurs, the
value is find; otherwise, the value is empty. You can use this
function in a conditional to test for the presence of a specific
substring in a given string. Thus, the two examples,
$(findstring a,a b c)
$(findstring a,b c)
produce the values `a' and `' (the empty string),
respectively. See section Conditionals that Test Flags, for a practical application of
findstring.
$(filter pattern...,text)
Returns all whitespace-separated words in text that do match
any of the pattern words, removing any words that do not
match. The patterns are written using `%', just like the patterns
used in the patsubst function above.
The filter function can be used to separate out different types
of strings (such as file names) in a variable. For example:
says that `foo' depends of `foo.c', `bar.c',
`baz.s' and `ugh.h' but only `foo.c', `bar.c' and
`baz.s' should be specified in the command to the
compiler.
$(filter-out pattern...,text)
Returns all whitespace-separated words in text that do not
match any of the pattern words, removing the words that do
match one or more. This is the exact opposite of the filter
function.
Removes all whitespace-separated words in text that do
match the pattern words, returning only the words that do
not match. This is the exact opposite of the filter
function.
For example, given:
the following generates a list which contains all the object files not
in `mains':
$(filter-out $(mains),$(objects))
$(sort list)
Sorts the words of list in lexical order, removing duplicate
words. The output is a list of words separated by single spaces.
Thus,
$(sort foo bar lose)
returns the value `bar foo lose'.
Incidentally, since sort removes duplicate words, you can use
it for this purpose even if you don't care about the sort order.
Here is a realistic example of the use of subst and
patsubst. Suppose that a makefile uses the VPATH variable
to specify a list of directories that make should search for
prerequisite files
(see section VPATH: Search Path for All Prerequisites).
This example shows how to
tell the C compiler to search for header files in the same list of
directories.
The value of VPATH is a list of directories separated by colons,
such as `src:../headers'. First, the subst function is used to
change the colons to spaces:
$(subst :, ,$(VPATH))
This produces `src ../headers'. Then patsubst is used to turn
each directory name into a `-I' flag. These can be added to the
value of the variable CFLAGS, which is passed automatically to the C
compiler, like this:
The effect is to append the text `-Isrc -I../headers' to the
previously given value of CFLAGS. The override directive is
used so that the new value is assigned even if the previous value of
CFLAGS was specified with a command argument (see section The override Directive).
Several of the built-in expansion functions relate specifically to
taking apart file names or lists of file names.
Each of the following functions performs a specific transformation on a
file name. The argument of the function is regarded as a series of file
names, separated by whitespace. (Leading and trailing whitespace is
ignored.) Each file name in the series is transformed in the same way and
the results are concatenated with single spaces between them.
$(dir names...)
Extracts the directory-part of each file name in names. The
directory-part of the file name is everything up through (and
including) the last slash in it. If the file name contains no slash,
the directory part is the string `./'. For example,
$(dir src/foo.c hacks)
produces the result `src/ ./'.
$(notdir names...)
Extracts all but the directory-part of each file name in names.
If the file name contains no slash, it is left unchanged. Otherwise,
everything through the last slash is removed from it.
A file name that ends with a slash becomes an empty string. This is
unfortunate, because it means that the result does not always have the
same number of whitespace-separated file names as the argument had;
but we do not see any other valid alternative.
For example,
$(notdir src/foo.c hacks)
produces the result `foo.c hacks'.
$(suffix names...)
Extracts the suffix of each file name in names. If the file name
contains a period, the suffix is everything starting with the last
period. Otherwise, the suffix is the empty string. This frequently
means that the result will be empty when names is not, and if
names contains multiple file names, the result may contain fewer
file names.
For example,
$(suffix src/foo.c src-1.0/bar.c hacks)
produces the result `.c .c'.
$(basename names...)
Extracts all but the suffix of each file name in names. If the
file name contains a period, the basename is everything starting up to
(and not including) the last period. Periods in the directory part are
ignored. If there is no period, the basename is the entire file name.
For example,
$(basename src/foo.c src-1.0/bar hacks)
produces the result `src/foo src-1.0/bar hacks'.
$(addsuffix suffix,names...)
The argument names is regarded as a series of names, separated
by whitespace; suffix is used as a unit. The value of
suffix is appended to the end of each individual name and the
resulting larger names are concatenated with single spaces between
them. For example,
$(addsuffix .c,foo bar)
produces the result `foo.c bar.c'.
$(addprefix prefix,names...)
The argument names is regarded as a series of names, separated
by whitespace; prefix is used as a unit. The value of
prefix is prepended to the front of each individual name and the
resulting larger names are concatenated with single spaces between
them. For example,
$(addprefix src/,foo bar)
produces the result `src/foo src/bar'.
$(join list1,list2)
Concatenates the two arguments word by word: the two first words (one
from each argument) concatenated form the first word of the result, the
two second words form the second word of the result, and so on. So the
nth word of the result comes from the nth word of each
argument. If one argument has more words that the other, the extra
words are copied unchanged into the result.
For example, `$(join a b,.c .o)' produces `a.c b.o'.
Whitespace between the words in the lists is not preserved; it is
replaced with a single space.
This function can merge the results of the dir and
notdir functions, to produce the original list of files which
was given to those two functions.
$(word n,text)
Returns the nth word of text. The legitimate values of
n start from 1. If n is bigger than the number of words
in text, the value is empty. For example,
$(word 2, foo bar baz)
returns `bar'.
$(wordlist s,e,text)
Returns the list of words in text starting with word s and
ending with word e (inclusive). The legitimate values of s
and e start from 1. If s is bigger than the number of words
in text, the value is empty. If e is bigger than the number
of words in text, words up to the end of text are returned.
If s is greater than e, nothing is returned. For example,
$(wordlist 2, 3, foo bar baz)
returns `bar baz'.
$(words text)
Returns the number of words in text.
Thus, the last word of text is
$(word $(words text),text).
$(firstword names...)
The argument names is regarded as a series of names, separated
by whitespace. The value is the first name in the series. The rest
of the names are ignored.
For example,
$(firstword foo bar)
produces the result `foo'. Although $(firstword
text) is the same as $(word 1,text), the
firstword function is retained for its simplicity.
$(wildcard pattern)
The argument pattern is a file name pattern, typically containing
wildcard characters (as in shell file name patterns). The result of
wildcard is a space-separated list of the names of existing files
that match the pattern.
See section Using Wildcard Characters in File Names.
The foreach function is very different from other functions. It
causes one piece of text to be used repeatedly, each time with a different
substitution performed on it. It resembles the for command in the
shell sh and the foreach command in the C-shell csh.
The syntax of the foreach function is:
$(foreach var,list,text)
The first two arguments, var and list, are expanded before
anything else is done; note that the last argument, text, is
not expanded at the same time. Then for each word of the expanded
value of list, the variable named by the expanded value of var
is set to that word, and text is expanded. Presumably text
contains references to that variable, so its expansion will be different
each time.
The result is that text is expanded as many times as there are
whitespace-separated words in list. The multiple expansions of
text are concatenated, with spaces between them, to make the result
of foreach.
This simple example sets the variable `files' to the list of all files
in the directories in the list `dirs':
dirs := a b c d
files := $(foreach dir,$(dirs),$(wildcard $(dir)/*))
Here text is `$(wildcard $(dir)/*)'. The first repetition
finds the value `a' for dir, so it produces the same result
as `$(wildcard a/*)'; the second repetition produces the result
of `$(wildcard b/*)'; and the third, that of `$(wildcard c/*)'.
This example has the same result (except for setting `dirs') as
the following example:
files := $(wildcard a/* b/* c/* d/*)
When text is complicated, you can improve readability by giving it
a name, with an additional variable:
find_files = $(wildcard $(dir)/*)
dirs := a b c d
files := $(foreach dir,$(dirs),$(find_files))
Here we use the variable find_files this way. We use plain `='
to define a recursively-expanding variable, so that its value contains an
actual function call to be reexpanded under the control of foreach;
a simply-expanded variable would not do, since wildcard would be
called only once at the time of defining find_files.
The foreach function has no permanent effect on the variable
var; its value and flavor after the foreach function call are
the same as they were beforehand. The other values which are taken from
list are in effect only temporarily, during the execution of
foreach. The variable var is a simply-expanded variable
during the execution of foreach. If var was undefined
before the foreach function call, it is undefined after the call.
See section The Two Flavors of Variables.
You must take care when using complex variable expressions that result in
variable names because many strange things are valid variable names, but
are probably not what you intended. For example,
files := $(foreach Esta escrito en espanol!,b c ch,$(find_files))
might be useful if the value of find_files references the variable
whose name is `Esta escrito en espanol!' (es un nombre bastante largo,
no?), but it is more likely to be a mistake.
The if function provides support for conditional expansion in a
functional context (as opposed to the GNU make makefile
conditionals such as ifeq (see section Syntax of Conditionals).
An if function call can contain either two or three arguments:
$(if condition,then-part[,else-part])
The first argument, condition, first has all preceding and
trailing whitespace stripped, then is expanded. If it expands to any
non-empty string, then the condition is considered to be true. If it
expands to an empty string, the condition is considered to be false.
If the condition is true then the second argument, then-part, is
evaluated and this is used as the result of the evaluation of the entire
if function.
If the condition is false then the third argument, else-part, is
evaluated and this is the result of the if function. If there is
no third argument, the if function evaluates to nothing (the
empty string).
Note that only one of the then-part or the else-part will be
evaluated, never both. Thus, either can contain side-effects (such as
shell function calls, etc.)
The call function is unique in that it can be used to create new
parameterized functions. You can write a complex expression as the
value of a variable, then use call to expand it with different
values.
The syntax of the call function is:
$(call variable,param,param,...)
When make expands this function, it assigns each param to
temporary variables $(1), $(2), etc. The variable
$(0) will contain variable. There is no maximum number of
parameter arguments. There is no minimum, either, but it doesn't make
sense to use call with no parameters.
Then variable is expanded as a make variable in the context
of these temporary assignments. Thus, any reference to $(1) in
the value of variable will resolve to the first param in the
invocation of call.
Note that variable is the name of a variable, not a
reference to that variable. Therefore you would not normally use
a `$' or parentheses when writing it. (You can, however, use a
variable reference in the name if you want the name not to be a
constant.)
If variable is the name of a builtin function, the builtin function
is always invoked (even if a make variable by that name also
exists).
The call function expands the param arguments before
assigning them to temporary variables. This means that variable
values containing references to builtin functions that have special
expansion rules, like foreach or if, may not work as you
expect.
Some examples may make this clearer.
This macro simply reverses its arguments:
reverse = $(2) $(1)
foo = $(call reverse,a,b)
Here foo will contain `b a'.
This one is slightly more interesting: it defines a macro to search for
the first instance of a program in PATH:
The call function can be nested. Each recursive invocation gets
its own local values for $(1), etc. that mask the values of
higher-level call. For example, here is an implementation of a
map function:
map = $(foreach a,$(2),$(call $(1),$(a)))
Now you can map a function that normally takes only one argument,
such as origin, to multiple values in one step:
o = $(call map,origin,o map MAKE)
and end up with o containing something like `file file default'.
A final caution: be careful when adding whitespace to the arguments to
call. As with other functions, any whitespace contained in the
second and subsequent arguments is kept; this can cause strange
effects. It's generally safest to remove all extraneous whitespace when
providing parameters to call.
The origin function is unlike most other functions in that it does
not operate on the values of variables; it tells you something about
a variable. Specifically, it tells you where it came from.
The syntax of the origin function is:
$(origin variable)
Note that variable is the name of a variable to inquire about;
not a reference to that variable. Therefore you would not normally
use a `$' or parentheses when writing it. (You can, however, use a
variable reference in the name if you want the name not to be a constant.)
The result of this function is a string telling you how the variable
variable was defined:
`undefined'
if variable was never defined.
`default'
if variable has a default definition, as is usual with CC
and so on. See section Variables Used by Implicit Rules.
Note that if you have redefined a default variable, the origin
function will return the origin of the later definition.
`environment'
if variable was defined as an environment variable and the
`-e' option is not turned on (see section Summary of Options).
`environment override'
if variable was defined as an environment variable and the
`-e' option is turned on (see section Summary of Options).
`file'
if variable was defined in a makefile.
`command line'
if variable was defined on the command line.
`override'
if variable was defined with an override directive in a
makefile (see section The override Directive).
`automatic'
if variable is an automatic variable defined for the
execution of the commands for each rule
(see section Automatic Variables).
This information is primarily useful (other than for your curiosity) to
determine if you want to believe the value of a variable. For example,
suppose you have a makefile `foo' that includes another makefile
`bar'. You want a variable bletch to be defined in `bar'
if you run the command `make -f bar', even if the environment contains
a definition of bletch. However, if `foo' defined
bletch before including `bar', you do not want to override that
definition. This could be done by using an override directive in
`foo', giving that definition precedence over the later definition in
`bar'; unfortunately, the override directive would also
override any command line definitions. So, `bar' could
include:
The shell function is unlike any other function except the
wildcard function
(see section The Function wildcard) in that it
communicates with the world outside of make.
The shell function performs the same function that backquotes
(``') perform in most shells: it does command expansion. This
means that it takes an argument that is a shell command and returns the
output of the command. The only processing make does on the result,
before substituting it into the surrounding text, is to convert each
newline or carriage-return / newline pair to a single space. It also
removes the trailing (carriage-return and) newline, if it's the last
thing in the result.
The commands run by calls to the shell function are run when the
function calls are expanded. In most cases, this is when the makefile is
read in. The exception is that function calls in the commands of the rules
are expanded when the commands are run, and this applies to shell
function calls like all others.
Here are some examples of the use of the shell function:
contents := $(shell cat foo)
sets contents to the contents of the file `foo', with a space
(rather than a newline) separating each line.
files := $(shell echo *.c)
sets files to the expansion of `*.c'. Unless make is
using a very strange shell, this has the same result as
`$(wildcard *.c)'.
These functions control the way make runs. Generally, they are used to
provide information to the user of the makefile or to cause make to stop
if some sort of environmental error is detected.
$(error text...)
Generates a fatal error where the message is text. Note that the
error is generated whenever this function is evaluated. So, if you put
it inside a command script or on the right side of a recursive variable
assignment, it won't be evaluated until later. The text will be
expanded before the error is generated.
For example,
ifdef ERROR1
$(error error is $(ERROR1))
endif
will generate a fatal error during the read of the makefile if the
make variable ERROR1 is defined. Or,
ERR = $(error found an error!)
.PHONY: err
err: ; $(ERR)
will generate a fatal error while make is running, if the
err target is invoked.
$(warning text...)
This function works similarly to the error function, above,
except that make doesn't exit. Instead, text is expanded
and the resulting message is displayed, but processing of the makefile
continues.
The result of the expansion of this function is the empty string.
A makefile that says how to recompile a program can be used in more
than one way. The simplest use is to recompile every file that is out
of date. Usually, makefiles are written so that if you run
make with no arguments, it does just that.
But you might want to update only some of the files; you might want to use
a different compiler or different compiler options; you might want just to
find out which files are out of date without changing them.
By giving arguments when you run make, you can do any of these
things and many others.
The exit status of make is always one of three values:
0
The exit status is zero if make is successful.
2
The exit status is two if make encounters any errors.
It will print messages describing the particular errors.
1
The exit status is one if you use the `-q' flag and make
determines that some target is not already up to date.
See section Instead of Executing the Commands.
The way to specify the name of the makefile is with the `-f' or
`--file' option (`--makefile' also works). For example,
`-f altmake' says to use the file `altmake' as the makefile.
If you use the `-f' flag several times and follow each `-f'
with an argument, all the specified files are used jointly as
makefiles.
If you do not use the `-f' or `--file' flag, the default is
to try `GNUmakefile', `makefile', and `Makefile', in
that order, and use the first of these three which exists or can be made
(see section Writing Makefiles).
The goals are the targets that make should strive ultimately
to update. Other targets are updated as well if they appear as
prerequisites of goals, or prerequisites of prerequisites of goals, etc.
By default, the goal is the first target in the makefile (not counting
targets that start with a period). Therefore, makefiles are usually
written so that the first target is for compiling the entire program or
programs they describe. If the first rule in the makefile has several
targets, only the first target in the rule becomes the default goal, not
the whole list.
You can specify a different goal or goals with arguments to make.
Use the name of the goal as an argument. If you specify several goals,
make processes each of them in turn, in the order you name them.
Any target in the makefile may be specified as a goal (unless it
starts with `-' or contains an `=', in which case it will be
parsed as a switch or variable definition, respectively). Even
targets not in the makefile may be specified, if make can find
implicit rules that say how to make them.
Make will set the special variable MAKECMDGOALS to the
list of goals you specified on the command line. If no goals were given
on the command line, this variable is empty. Note that this variable
should be used only in special circumstances.
An example of appropriate use is to avoid including `.d' files
during clean rules (see section Generating Prerequisites Automatically), so
make won't create them only to immediately remove them
again:
sources = foo.c bar.c
ifneq ($(MAKECMDGOALS),clean)
include $(sources:.c=.d)
endif
One use of specifying a goal is if you want to compile only a part of
the program, or only one of several programs. Specify as a goal each
file that you wish to remake. For example, consider a directory containing
several programs, with a makefile that starts like this:
.PHONY: all
all: size nm ld ar as
If you are working on the program size, you might want to say
`make size' so that only the files of that program are recompiled.
Another use of specifying a goal is to make files that are not normally
made. For example, there may be a file of debugging output, or a
version of the program that is compiled specially for testing, which has
a rule in the makefile but is not a prerequisite of the default goal.
Another use of specifying a goal is to run the commands associated with
a phony target (see section Phony Targets) or empty target (see section Empty Target Files to Record Events). Many makefiles contain
a phony target named `clean' which deletes everything except source
files. Naturally, this is done only if you request it explicitly with
`make clean'. Following is a list of typical phony and empty
target names. See section Standard Targets for Users, for a detailed list of all the
standard target names which GNU software packages use.
`all'
Make all the top-level targets the makefile knows about.
`clean'
Delete all files that are normally created by running make.
`mostlyclean'
Like `clean', but may refrain from deleting a few files that people
normally don't want to recompile. For example, the `mostlyclean'
target for GCC does not delete `libgcc.a', because recompiling it
is rarely necessary and takes a lot of time.
`distclean'
`realclean'
`clobber'
Any of these targets might be defined to delete more files than
`clean' does. For example, this would delete configuration files
or links that you would normally create as preparation for compilation,
even if the makefile itself cannot create these files.
`install'
Copy the executable file into a directory that users typically search
for commands; copy any auxiliary files that the executable uses into
the directories where it will look for them.
`print'
Print listings of the source files that have changed.
`tar'
Create a tar file of the source files.
`shar'
Create a shell archive (shar file) of the source files.
`dist'
Create a distribution file of the source files. This might
be a tar file, or a shar file, or a compressed version of one of the
above, or even more than one of the above.
`TAGS'
Update a tags table for this program.
`check'
`test'
Perform self tests on the program this makefile builds.
The makefile tells make how to tell whether a target is up to date,
and how to update each target. But updating the targets is not always
what you want. Certain options specify other activities for make.
`-n'
`--just-print'
`--dry-run'
`--recon'
"No-op". The activity is to print what commands would be used to make
the targets up to date, but not actually execute them.
`-t'
`--touch'
"Touch". The activity is to mark the targets as up to date without
actually changing them. In other words, make pretends to compile
the targets but does not really change their contents.
`-q'
`--question'
"Question". The activity is to find out silently whether the targets
are up to date already; but execute no commands in either case. In other
words, neither compilation nor output will occur.
`-W file'
`--what-if=file'
`--assume-new=file'
`--new-file=file'
"What if". Each `-W' flag is followed by a file name. The given
files' modification times are recorded by make as being the present
time, although the actual modification times remain the same.
You can use the `-W' flag in conjunction with the `-n' flag
to see what would happen if you were to modify specific files.
With the `-n' flag, make prints the commands that it would
normally execute but does not execute them.
With the `-t' flag, make ignores the commands in the rules
and uses (in effect) the command touch for each target that needs to
be remade. The touch command is also printed, unless `-s' or
.SILENT is used. For speed, make does not actually invoke
the program touch. It does the work directly.
With the `-q' flag, make prints nothing and executes no
commands, but the exit status code it returns is zero if and only if the
targets to be considered are already up to date. If the exit status is
one, then some updating needs to be done. If make encounters an
error, the exit status is two, so you can distinguish an error from a
target that is not up to date.
It is an error to use more than one of these three flags in the same
invocation of make.
The `-n', `-t', and `-q' options do not affect command
lines that begin with `+' characters or contain the strings
`$(MAKE)' or `${MAKE}'. Note that only the line containing
the `+' character or the strings `$(MAKE)' or `${MAKE}'
is run regardless of these options. Other lines in the same rule are
not run unless they too begin with `+' or contain `$(MAKE)' or
`${MAKE}' (See section How the MAKE Variable Works.)
The `-W' flag provides two features:
If you also use the `-n' or `-q' flag, you can see what
make would do if you were to modify some files.
Without the `-n' or `-q' flag, when make is actually
executing commands, the `-W' flag can direct make to act
as if some files had been modified, without actually modifying the
files.
Note that the options `-p' and `-v' allow you to obtain other
information about make or about the makefiles in use
(see section Summary of Options).
Sometimes you may have changed a source file but you do not want to
recompile all the files that depend on it. For example, suppose you add
a macro or a declaration to a header file that many other files depend
on. Being conservative, make assumes that any change in the
header file requires recompilation of all dependent files, but you know
that they do not need to be recompiled and you would rather not waste
the time waiting for them to compile.
If you anticipate the problem before changing the header file, you can
use the `-t' flag. This flag tells make not to run the
commands in the rules, but rather to mark the target up to date by
changing its last-modification date. You would follow this procedure:
Use the command `make' to recompile the source files that really
need recompilation.
Make the changes in the header files.
Use the command `make -t' to mark all the object files as
up to date. The next time you run make, the changes in the
header files will not cause any recompilation.
If you have already changed the header file at a time when some files
do need recompilation, it is too late to do this. Instead, you can
use the `-o file' flag, which marks a specified file as
"old" (see section Summary of Options). This means
that the file itself will not be remade, and nothing else will be
remade on its account. Follow this procedure:
Recompile the source files that need compilation for reasons independent
of the particular header file, with `make -o headerfile'.
If several header files are involved, use a separate `-o' option
for each header file.
An argument that contains `=' specifies the value of a variable:
`v=x' sets the value of the variable v to x.
If you specify a value in this way, all ordinary assignments of the same
variable in the makefile are ignored; we say they have been
overridden by the command line argument.
The most common way to use this facility is to pass extra flags to
compilers. For example, in a properly written makefile, the variable
CFLAGS is included in each command that runs the C compiler, so a
file `foo.c' would be compiled something like this:
cc -c $(CFLAGS) foo.c
Thus, whatever value you set for CFLAGS affects each compilation
that occurs. The makefile probably specifies the usual value for
CFLAGS, like this:
CFLAGS=-g
Each time you run make, you can override this value if you
wish. For example, if you say `make CFLAGS='-g -O'', each C
compilation will be done with `cc -c -g -O'. (This illustrates
how you can use quoting in the shell to enclose spaces and other
special characters in the value of a variable when you override it.)
The variable CFLAGS is only one of many standard variables that
exist just so that you can change them this way. See section Variables Used by Implicit Rules, for a complete list.
You can also program the makefile to look at additional variables of your
own, giving the user the ability to control other aspects of how the
makefile works by changing the variables.
When you override a variable with a command argument, you can define either
a recursively-expanded variable or a simply-expanded variable. The
examples shown above make a recursively-expanded variable; to make a
simply-expanded variable, write `:=' instead of `='. But, unless
you want to include a variable reference or function call in the
value that you specify, it makes no difference which kind of
variable you create.
There is one way that the makefile can change a variable that you have
overridden. This is to use the override directive, which is a line
that looks like this: `override variable = value'
(see section The override Directive).
Normally, when an error happens in executing a shell command, make
gives up immediately, returning a nonzero status. No further commands are
executed for any target. The error implies that the goal cannot be
correctly remade, and make reports this as soon as it knows.
When you are compiling a program that you have just changed, this is not
what you want. Instead, you would rather that make try compiling
every file that can be tried, to show you as many compilation errors
as possible.
On these occasions, you should use the `-k' or
`--keep-going' flag. This tells make to continue to
consider the other prerequisites of the pending targets, remaking them
if necessary, before it gives up and returns nonzero status. For
example, after an error in compiling one object file, `make -k'
will continue compiling other object files even though it already
knows that linking them will be impossible. In addition to continuing
after failed shell commands, `make -k' will continue as much as
possible after discovering that it does not know how to make a target
or prerequisite file. This will always cause an error message, but
without `-k', it is a fatal error (see section Summary of Options).
The usual behavior of make assumes that your purpose is to get the
goals up to date; once make learns that this is impossible, it might
as well report the failure immediately. The `-k' flag says that the
real purpose is to test as much as possible of the changes made in the
program, perhaps to find several independent problems so that you can
correct them all before the next attempt to compile. This is why Emacs'
M-x compile command passes the `-k' flag by default.
Here is a table of all the options make understands:
`-b'
`-m'
These options are ignored for compatibility with other versions of make.
`-C dir'
`--directory=dir'
Change to directory dir before reading the makefiles. If multiple
`-C' options are specified, each is interpreted relative to the
previous one: `-C / -C etc' is equivalent to `-C /etc'.
This is typically used with recursive invocations of make
(see section Recursive Use of make).
`-d'
Print debugging information in addition to normal processing. The
debugging information says which files are being considered for
remaking, which file-times are being compared and with what results,
which files actually need to be remade, which implicit rules are
considered and which are applied--everything interesting about how
make decides what to do. The -d option is equivalent to
`--debug=a' (see below).
`--debug[=options]'
Print debugging information in addition to normal processing. Various
levels and types of output can be chosen. With no arguments, print the
"basic" level of debugging. Possible arguments are below; only the
first character is considered, and values must be comma- or
space-separated.
a (all)
All types of debugging output are enabled. This is equivalent to using
`-d'.
b (basic)
Basic debugging prints each target that was found to be out-of-date, and
whether the build was successful or not.
v (verbose)
A level above `basic'; includes messages about which makefiles were
parsed, prerequisites that did not need to be rebuilt, etc. This option
also enables `basic' messages.
i (implicit)
Prints messages describing the implicit rule searches for each target.
This option also enables `basic' messages.
j (jobs)
Prints messages giving details on the invocation of specific subcommands.
m (makefile)
By default, the above messages are not enabled while trying to remake
the makefiles. This option enables messages while rebuilding makefiles,
too. Note that the `all' option does enable this option. This
option also enables `basic' messages.
`-e'
`--environment-overrides'
Give variables taken from the environment precedence
over variables from makefiles.
See section Variables from the Environment.
`-f file'
`--file=file'
`--makefile=file'
Read the file named file as a makefile.
See section Writing Makefiles.
`-h'
`--help'
Remind you of the options that make understands and then exit.
`-i'
`--ignore-errors'
Ignore all errors in commands executed to remake files.
See section Errors in Commands.
`-I dir'
`--include-dir=dir'
Specifies a directory dir to search for included makefiles.
See section Including Other Makefiles. If several `-I'
options are used to specify several directories, the directories are
searched in the order specified.
`-j [jobs]'
`--jobs[=jobs]'
Specifies the number of jobs (commands) to run simultaneously. With no
argument, make runs as many jobs simultaneously as possible. If
there is more than one `-j' option, the last one is effective.
See section Parallel Execution,
for more information on how commands are run.
Note that this option is ignored on MS-DOS.
`-k'
`--keep-going'
Continue as much as possible after an error. While the target that
failed, and those that depend on it, cannot be remade, the other
prerequisites of these targets can be processed all the same.
See section Testing the Compilation of a Program.
`-l [load]'
`--load-average[=load]'
`--max-load[=load]'
Specifies that no new jobs (commands) should be started if there are
other jobs running and the load average is at least load (a
floating-point number). With no argument, removes a previous load
limit. See section
