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When creating a new design project, create a new directory where all the design data should reside. The directory should be placed under a directory where all other design projects are kept.
Using Windows Explorer, create a new directory, "Projects", to hold all your design projects. Under the "Projects" directory, create a design project directory named "Tutorial".
Launch the VHDLMG and invoke File -- New Project... (Ctrl+N) from main menu. Browse to the "Tutorial" directory just created and enter a new project name, in this case, "Tutorial.vmg". A new project window is then shown. An icon named "ProjectA" at the upper left corner of the window denotes the subdirectory where all the VHDL source files reside. You can change the subdirectory name by highlighting the word and pressing space bar. Change the subdirectory to "VHDLMG Tutorial".
Figure below shows the recommended directory structure. Under the design project directory "Tutorial", "VHDLMG Tutorial" holds VHDL source files created in the VHDLMG. "Express Tutorial" will be created later to contain design synthesis files using the Synopsys FPGA Express. "Mp" will be created later to hold design implementation files using the Altera MAX+Plus II.
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