TUTORIAL


Content

1. Creating a new project
2. Creating a new design module
3. Editing interface ports
4. Editing and analyzing VHDL code
5. Creating bottom-up design
6. Drawing block diagram
7. Parameterized design entry
8. Synthesizing design module
9. Storing module to library
10. Creating top-down design
11. Generating design documentation
12. Using Altera LPM RAM
13. Using Altera LPM ROM

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Prepared by Koay Kah Hoe
Last modified: 20 January 2000

VHDL Module Generator Version 1.08
Copyright © 2000 Universiti Teknologi Malaysia

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