Using Altera LPM RAM

LPM modules in Altera MAX+plus II are accessible from the VHDLMG using predefined module. Predefined module is inserted by invoking Insert Predefined Module (F3), or inserted from block diagram by placing Predefined Module (Ctrl+Alt+P).

This example demonstrates usage of an LPM RAM module. Add a normal module, "ram", at the top level design hierarchy. Under the ram module, insert LPM_RAM_DQ module from predefined module library under "LPM Components" category. Set parameters of the LPM module as shown below. For detailed description on usage of LPM modules, please refer to Altera MAX+plus II help system on Megafunctions/LPM.

At the ram module, set its interface ports as below:

Edit the ram module's VHDL content as shown below:

architecture ram_arch of ram is signal HIGH : STD_LOGIC; .... .... begin HIGH <= '1'; U_LPM_RAM_DQ: LPM_RAM_DQ port map (DATA, ADDRESS, WE, HIGH, HIGH, Q); end ram_arch;

You can then generate the ram module from the VHDLMG for synthesis and implementation following normal procedures.