HOME PREVIOUS NEXT

Synthesizing design module

If the digit module has not been analyzed, analyze it. Open the VHDL file of the module. Notice that the parameter entries, interface ports, component declarations and component instantiations have been added by the VHDLMG automatically in the code. Add an internal signal at architecture declarative part and modify the architecture content as shown below:

architecture digit_arch of digit is

    signal HEXint : UNSIGNED(3 downto 0);

    ....
    ....

begin

    U_Counter: Counter
        port map (START, EN, HEXint, CLK);

    U_Hex2LED: Hex2LED
        port map (HEXint, LED);

    HEX <= HEXint;

end digit_arch;

After editing, close the VHDL file and analyze the module. If no error is encountered, the module is now ready to be synthesized. Before generating synthesizable VHDL file, check the Destination folder parameter at the parameter list of the first item in design hierarchy explorer. Perferably, it is set to the same directory as the project directory.

Select the digit module at the design hierarchy explorer and invoke Module -- Generate (F9). The VHDL source codes are combined into one file with the filename digit.vhd. The next step is to synthesize the generated VHDL file. Invoke Tools -- Design Flow (Ctrl+D). A design flow window is opened. Select the Synthesis icon to launch the FPGA Express.

In the FPGA Express, create a new project at the same project directory and name it "Express Tutorial". Then, in the "Add Sources" dialog, select the generated synthesizable VHDL file digit.vhd (*NOT the source VHDL). The software will analyze the file. If no error is encountered, a tick mark is shown at the left of the VHDL filename in the "Design Sources" window. Open the tree view, 3 modules are shown -- digit, Hex2LED, and Counter. Select the digit module and invoke Synthesis -- Create Implementation.... A dialog box is shown. In the "Vendor" dropdown box, select Altera. Select an appropriate Altera device. Other settings can be kept unchanged. Click the OK button. The software will run the synthesis process. If the process is successful, two items are added at the "Chips" window. Select the second item (digit-Optimized) and invoke Synthesis -- Export Netlist.... Create a new directory under the project directory using Explorer (Eg. C:\Projects\Tutorial\Mp) and select it in the "Export Directory" item in the "Export" dialog. Click OK to export the netlist. Netlist file in EDF format and several other files are generated. Synthesis process is completed, close the FPGA Express.

Back to the VHDLMG, click the Implementation icon in the design flow window to launch the MAX+Plus II software. Select the EDF netlist as the project, then compile and simulate the design.

Back to the VHDLMG again, click the Design Entry icon to go back to the design entry window. At the "Synthesis" parameter at the parameter list of the first item, you can optionally set it to the FPGA Express project file created (Eg. C:\Projects\Tutorial\Express Tutorial\Express Tutorial.exp). The next time launching the software through the design flow window, the project will be opened automatically.


HOME PREVIOUS NEXT
1