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Parameterized design entry

Parameterized design entry is one of the major features of the VHDLMG. This feature enables generic description of designs, thus facilitates reusability of modules. The tool allows parameter insertion and specification through graphical user interface at the parameter editor on the right of design hierarchy explorer. Various types of parameters are provided, including:

Refer to user manual for detailed description and usage of each parameter. You can also take a look at VHDL codes of library modules for usage of these parameters.

Notice that the first item in the parameter list of any module is not actually parameter, it denotes the module name and VHDL filename. Activating it by double clicking using mouse or hitting Enter key to open the VHDL file.

Open the VHDL file for the Counter module, examine the code, especially on how various parameters are used in this module. Select the Counter module at the design hierarchy explorer, set its parameter list as below. An interesting feature of the tool is that parameters can be passed from upper hierarchies. The "EndValue" parameter is not specified with an integer number, but another parameter at upper design hierarchy (in this case, using the same parameter name).

Select the digit module at the design hierarchy explorer. Insert the following two parameters to the module. This is done by right clicking using mouse to invoke popup menu or open the Parameter menu, then select desired parameter to add. To modify parameter name, double click on the item column of the corresponding parameter and specify a new parameter name.


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