RTR software is much like the general computing Operating Systems. The OS manages the system memory and schedules the programs in the multitasking environments, as well as RTR software that allocates hardware modules and pages them in and out of the FPGA according to the schedule and the flow of the program. These modules can be cached and relocated in the FPGA to get the optimal performance with minimum area. This is one of the advantages of the partial reconfiguration.
The relocation problem is a commonly known problem faced by the OS designers. They need to manage memory fragments and paging memory modules in and out of the physical memory to increase the size of the memory that can be used by the running applications beyond the available real memory. Module removal from the cache and relocation algorithm used in RTR software are adopted from the OS's algorithms1, but the only difference between them is that the hardware modules are two dimensional modules while the memory modules are one dimensional, which makes the RTR software more complicated and less efficient [16]. Some solutions were discussed in the DISC project [17,18].