Total vs. Partial reconfiguration

One of the features of the partially reconfigured FPGAs, is that the size of the bit-stream is proportional to the size of the reconfigured resources. This means that as the size of the bit-stream decreases, the speed of the reconfiguration increases. As a result, the configuration of the partially reconfigured systems is faster than the total reconfigurable systems.
The algorithm is divided into time-exclusive segments ``time independent partitions'' in the totally reconfigured systems. While when the partial reconfiguration is used the it is divided into functional groups that can be loaded or removed independently [10]. The first method of division requires that the partitions must be of equal sizes because each partition will occupy the whole resources of the FPGA. This may increase the difficulty of the partitioning process unless there is well defined partitions in the algorithm as in the RRANN project where the system is divided into three independent logical partitions that are loaded sequentially to the system [7,16]. This means that the density of the partially reconfigured systems is increased due to the extra utilization of the idle circuitry.
The state of the system and the intermediate results between different configurations must be considered between loading and unloading these configurations. The total reconfiguration scheme uses external memory to save these information. The other scheme needs less or no memory to store these results because most of their driving circuits remain on the hardware.
One of the most advantages of partially reconfigured systems is that the partitions can be located on the FPGA resources during the run-time to provide extra performance and to increase the utilization of the resources that may be reduced due to multiple loading and unloading of hardware modules. The concept or hardware relocation complicates the software design, refer to section 5.3 on page .